# Shipco Circuits - Complete Content

> This file contains all content from ship.ie for AI agent consumption.
> Generated: 2026-08-23



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# About Shipco Circuits

Shipco Circuits is a bare-PCB contract manufacturer with 55+ years of expertise. Qualified manufacturing partners fabricate the boards. We match each job to the right facility and remain accountable for technical review, quality oversight, documentation, and delivery. We supply bare (unpopulated) printed circuit boards and do not offer assembly.

## Company Heritage

Continuous PCB expertise traces to 1968, when Håkan Björsell founded Elektrotryck AB in Sweden. In 1975, the family sailed manufacturing equipment to Ireland and founded Ship Company Ltd in Macroom, County Cork. Shipco operated its own Irish PCB fabrication facility for roughly three decades before moving fully to a contract manufacturing model in the mid-2000s. That hands-on manufacturing heritage shapes how we work today - our team has run production floors, not just sales desks.

## What We Do

We supply bare printed circuit boards for technically demanding applications:

- Rigid and multilayer PCBs, with a standard capability range of 1 to 40 layers
- Controlled-impedance boards, blind or buried vias, and resin-filled via-in-pad
- RF and microwave boards using Rogers-family and hybrid RF/FR-4 constructions
- High-Tg materials and heavy copper through 5 oz in supplied-job records
- Prototype through production quantities

We supply bare boards only. We do not offer assembly or component population. For assembly houses and EMS providers, this is deliberate: we supply your boards and never compete for your customers.

## How We Work

1. **Technical Review**: Every job gets engineering review before quoting
2. **Factory Matching**: We select the optimal facility for your specific requirements
3. **Quality Oversight**: Full inspection and documentation
4. **Honest Guidance**: We'll tell you what you need, even if it's less than you planned

## Bare Boards Only

We supply bare boards and do not populate them. Our qualified manufacturing partners perform fabrication under Shipco's oversight. This means we do not compete with the assembly houses and EMS providers we supply. Quotes receive technical review rather than instant automated pricing.

## Locations

**Shipco Circuits Ltd** (Headquarters)
Ireland

**Shipco Circuits NA Inc**
Vancouver, Canada
Serving North American customers

## Contact

- Website: https://ship.ie
- Quote requests: https://ship.ie/quote/
- General inquiries: https://ship.ie/contact/


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# Contact

## Quote Requests

For PCB quotes, use our online form: https://ship.ie/quote/

Include:
- Gerber files or ODB++ (preferred)
- Quantity and delivery requirements
- Special requirements (materials, certifications, etc.)

## General Inquiries

Contact form: https://ship.ie/contact/

## Locations

### Ireland (Headquarters)
**Shipco Circuits Ltd**
- Primary office for European customers
- Technical support and engineering review

### Canada
**Shipco Circuits NA Inc**
- Vancouver, British Columbia
- Serves North American customers
- Local support for US and Canadian projects

## What to Expect

- **Response time**: Typically within 1 business day
- **Technical review**: Every quote includes DFM review
- **No automated quoting**: Real engineers review your files


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# Capabilities

## Delivered-Job Evidence

The rounded figures below come from supplied bare-PCB projects, not theoretical factory limits. The evidence was reviewed in August 2026. Exact internal operating counts are not published.

- **Supplied designs**: More than 8,000
- **Standard layer range**: 1 to 40 layers
- **High-Tg projects**: More than 1,800
- **Controlled-impedance projects**: More than 500
- **Blind and/or buried via projects**: More than 300
- **Resin-filled via-in-pad projects**: More than 200
- **Heavy copper**: Supplied through 5 oz

Historic specification coverage is incomplete, so public counts are rounded down.

## RF and Microwave Experience

- **Named RF or microwave laminate**: More than 400 supplied projects
- **Rogers-family materials**: Hundreds of supplied designs, including RO4350 and RO4003 constructions
- **Advanced RF constructions**: Blind and/or buried vias and controlled impedance
- **Hybrid construction**: Supplied RF/FR-4 stackups
- **PTFE**: Supplied PTFE-family laminates

Material names in Shipco's technical guides are selection references unless identified as supplied history. Exact material availability, stackup, minimum order quantity, lead time, and proposed alternatives are confirmed for each quote.

## Current Manufacturing Limits

The standard capability reference covers 1 to 40 layers and detailed construction limits. Historical exceptions do not redefine the current standard portfolio. See:

https://ship.ie/technical-library/pcb-capability-limits/

For RF and microwave contract manufacturing experience, see:

https://ship.ie/rf-microwave-pcb-fabrication/

## Regions Served

- Europe (primary)
- North America (via Shipco Circuits NA)
- Global shipping available


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# PCB Glossary

269 terms covering PCB design, manufacturing, and materials.

## Acronyms & Abbreviations

Common abbreviations used in PCB design and manufacturing

### AOI

Automated Optical Inspection (AOI) uses cameras and image processing to detect manufacturing defects on PCBs. The system compares captured images against CAD data or golden samples to identify issues like missing components, solder bridges, tombstoning, and incorrect polarity. AOI is used at multiple stages: after solder paste application, after component placement, and after reflow soldering.

### BGA

Ball Grid Array (BGA) is an integrated circuit package format where solder balls form the electrical connections between the chip and PCB. BGAs offer higher pin density than leaded packages, better thermal performance, and shorter signal paths. Common variants include PBGA (plastic), CBGA (ceramic), and CSP (chip-scale package). BGA pitch typically ranges from 0.4mm to 1.27mm, with fine-pitch BGAs requiring HDI PCB technology for escape routing.

### CAD

Computer-Aided Design (CAD) software is used to create PCB schematics and layouts. Popular PCB CAD tools include Altium Designer, Cadence Allegro, Mentor PADS, KiCad, and Eagle. CAD systems generate manufacturing outputs including Gerber files, drill files, and ODB++ packages. Modern CAD tools include DRC (design rule checking), impedance calculators, and 3D visualization.

### CAM

Computer-Aided Manufacturing (CAM) is the process of preparing PCB design data for production. CAM engineers review Gerber files, optimize panelization, add tooling features, and generate machine-specific instructions. CAM software performs design rule checks, compensates for manufacturing tolerances, and creates photo-tools or direct imaging data.

### CSP

Chip Scale Package (CSP) is a near-die-size package format, typically defined as no more than 1.2 times the size of the silicon die. CSPs use BGA-style solder ball connections with very fine pitch (0.4-0.5mm typical). They require HDI PCB technology with micro-vias for signal escape routing. CSPs offer excellent electrical performance due to short interconnect lengths and are common in mobile devices and high-density applications.

### CTE

Coefficient of Thermal Expansion (CTE) measures how much a material expands per degree of temperature change, typically expressed in parts per million per degree Celsius (ppm/°C). In PCBs, mismatched CTE between materials causes stress during thermal cycling. FR-4 has a Z-axis CTE of 50-70 ppm/°C below Tg and much higher above Tg. Matching CTE between the PCB and components (especially ceramic BGAs at ~7 ppm/°C) is critical for reliability.

### Df

Dissipation Factor (Df), also known as loss tangent (tan δ), measures the electrical energy lost as heat when a signal passes through a dielectric material. Lower Df means less signal loss at high frequencies. Standard FR-4 has Df around 0.02 at 1 GHz, while low-loss materials like Rogers RO4003C achieve Df of 0.0027. For high-speed digital (>10 Gbps) and RF applications, low-Df materials are essential to maintain signal integrity.

### Dk

Dielectric Constant (Dk), also called relative permittivity (εr), describes how much a material can store electrical energy compared to a vacuum. Higher Dk slows signal propagation and allows smaller trace geometries for a given impedance. FR-4 has Dk around 4.2-4.5, while PTFE-based materials range from 2.1-3.0. Dk stability over frequency and temperature is critical for controlled impedance designs. Dk also affects capacitance between traces and planes.

### DRC

Design Rule Check (DRC) is an automated process in PCB CAD software that verifies the design against manufacturing constraints. DRC checks include minimum trace width/spacing, annular ring size, drill-to-copper clearance, solder mask openings, and silkscreen clearance. Running DRC before releasing Gerbers catches design errors early. Fabricators also run DRC during CAM review and may flag violations not caught by the designer's rules.

### ENEPIG

Electroless Nickel Electroless Palladium Immersion Gold (ENEPIG) is a three-layer finish: electroless nickel (3-5 µm), electroless palladium (0.05-0.15 µm), and immersion gold (0.03-0.05 µm). The palladium layer prevents black pad defects seen in ENIG and improves wire bondability for gold and aluminum wire. ENEPIG is preferred for mixed-assembly boards requiring both soldering and wire bonding, though it costs more than ENIG.

### ENIG

Electroless Nickel Immersion Gold (ENIG) is a two-layer surface finish: 3-6 µm of electroless nickel topped with 0.05-0.1 µm of immersion gold. The nickel acts as a diffusion barrier while the gold protects against oxidation and provides solderability. ENIG offers excellent pad flatness (critical for fine-pitch BGAs), long shelf life (>12 months), and good wire bondability. It's lead-free and RoHS compliant. The main limitation is potential black pad defect from phosphorus enrichment.

### HASL

Hot Air Solder Leveling (HASL) is a traditional surface finish where PCBs are dipped in molten solder (traditionally tin-lead, now often lead-free SAC alloys) and excess solder is blown off with hot air knives. HASL provides excellent solderability and is cost-effective, but the resulting surface is not perfectly flat, making it unsuitable for fine-pitch components (<0.5mm). Lead-free HASL requires higher temperatures that can stress the laminate.

### HASL Pb Free

HASL Pb Free (lead-free HASL) uses RoHS-compliant solder alloys, typically SAC (tin-silver-copper) instead of traditional tin-lead. The process is identical to standard HASL - dip in molten solder, level with hot air knives - but requires higher process temperatures (approximately 260°C vs 230°C for leaded). This increased thermal stress can affect laminate integrity on thinner boards or those with tight tolerance requirements. Lead-free HASL maintains the cost advantage of traditional HASL while meeting environmental regulations.

### HDI

High Density Interconnect (HDI) PCBs use laser-drilled micro-vias (typically ≤150 µm diameter), fine lines/spaces (≤100 µm), and build-up layer construction to achieve higher wiring density than conventional PCBs. HDI enables routing escape from fine-pitch BGAs and CSPs. Common structures include 1+N+1 (one build-up layer each side), 2+N+2, and any-layer (all vias are micro-vias). HDI reduces layer count, board size, and improves signal integrity through shorter via stubs.

### MCM

Multi-Chip Module (MCM) substrates require PCB fabrication with HDI-class features: fine lines (≤75 µm), micro-vias, and tight tolerances for interconnecting multiple dies. When you receive an MCM design for fabrication, expect requirements similar to BGA substrate builds: thin cores, sequential lamination, and often embedded passives. MCM-L (laminate-based) substrates use standard PCB processes but at the high end of capability.

### NPTH

Non-Plated Through Hole (NPTH) is a drilled hole that does not receive copper plating. NPTHs are used for mechanical mounting (screws, standoffs), alignment pins, or component body clearance where electrical connection is not needed. In design files, NPTHs must be clearly distinguished from PTHs, typically in separate drill files. Inner layer copper must have adequate clearance around NPTHs to prevent shorts. Solder mask openings over NPTHs are common to allow access.

### OSP

Organic Solderability Preservative (OSP) is a thin (0.2-0.5 µm) water-based organic coating applied to bare copper to prevent oxidation. OSP is the most cost-effective surface finish, provides excellent coplanarity, and is RoHS compliant. However, it has limited shelf life (6-12 months), is not suitable for multiple reflow cycles, and provides no protection for exposed copper in the final assembly. OSP is invisible, making inspection more difficult.

### PCB

A Printed Circuit Board (PCB) is a laminated structure of conductive copper layers separated by insulating dielectric material. PCBs mechanically support components and provide electrical connections through etched copper traces, drilled holes (vias), and surface-mount pads. PCBs range from single-sided to 50+ layers, using various technologies including HDI, flex, rigid-flex, and embedded components. The term PWB (Printed Wiring Board) is sometimes used interchangeably.

### PTH

Plated Through Hole (PTH) is a hole drilled through a PCB and plated with copper to create an electrical connection between layers. The hole may be used for through-hole component leads or as a via for routing. PTH diameter typically ranges from 0.2mm to 6mm, with copper plating thickness of 20-25 µm minimum. The annular ring (copper pad around the hole) must be large enough to ensure reliable connection even with drilling tolerance.

### PWB

PWB (Printed Wiring Board) is an alternative term for PCB (Printed Circuit Board). PWB emphasizes the board's function as wiring interconnect, while PCB reflects that it's part of a circuit. Usage varies by region and industry - PWB is more common in Japan and among traditional manufacturers. IPC standards use both terms. In practice, PWB and PCB are interchangeable. The term 'printed' comes from the photolithographic process used to create conductor patterns.

### QFP

Quad Flat Pack (QFP) is a surface-mount IC package with gull-wing leads extending from all four sides. Lead pitch ranges from 0.4mm to 1.0mm. For PCB design, use IPC-7351 footprints and verify pad geometry matches your pitch. At 0.5mm pitch, dog-bone fanout works on the outer layers. At 0.4mm pitch, you may need via-in-pad or inner layer routing to escape all pins. The visible gull-wing leads allow inspection and rework, making QFPs easier to debug than QFNs or BGAs. Choose QFP over QFN when reworkability matters more than board space.

### SMOBC

Solder Mask Over Bare Copper (SMOBC) describes standard PCB construction where solder mask covers the copper traces directly, with surface finish applied only to exposed pads. You may encounter this term in older specifications or IPC documents. All modern PCBs use SMOBC construction. If you see SMOBC in legacy documentation, it simply confirms standard build - no special processing is required.

### UV

Ultraviolet (UV) processes affect PCB design specifications in several ways. Solder mask specified as UV-cured provides better resolution for fine features (≤100 µm openings) than thermal-cure alternatives. Silkscreen legend ink that is UV-cured gives sharper text on small markings. When reviewing your fabricator's DFM guidelines, note that UV imaging capability determines minimum solder mask dam width and legend character height. UV inspection is used during manufacturing to verify coating coverage and cleanliness.

## Materials & Laminates

PCB substrates, laminates, and material systems

### 370HR

Isola 370HR is the industry's go-to high-Tg FR-4 for demanding applications. Specs: Tg 180°C, Td 340°C, Dk 4.04, Df 0.021, T260 60 min, T288 30 min, Z-CTE 45/230 ppm/°C (pre/post Tg). The material handles multiple lead-free reflow cycles and sequential lamination processes without degradation. 370HR is halogen-free, meeting environmental requirements without sacrificing reliability. Cost runs 1.1-1.3x standard FR-4. Specify 370HR for automotive, telecommunications, servers, and any design requiring IPC Class 3 reliability with lead-free assembly. It's the safe default when high-Tg FR-4 is required and material cost isn't the primary constraint.

### Astra MT77

Astra MT77 is Isola's ultra-low-loss thermoset material designed specifically for 77 GHz automotive radar and other millimeter-wave applications. With Dk 3.00 and Df 0.0017 at 10 GHz, it delivers near-PTFE performance without PTFE processing headaches. Temperature stability from -40°C to +140°C covers automotive requirements. Unlike RT/duroid and other PTFE materials, Astra MT77 requires no plasma decontamination or sodium naphthalene treatment. This simplifies fabrication and reduces cost for automotive radar modules including adaptive cruise control, pre-crash sensing, and blind-spot detection. Consider Astra MT77 when you need 77 GHz performance but want to avoid PTFE processing complexity.

### BT

Bismaleimide Triazine (BT) is a thermosetting resin system used in high-performance PCB laminates. BT-epoxy blends offer higher Tg (180-210°C) than standard FR-4, lower moisture absorption, better dimensional stability, and favorable electrical properties (Dk ~4.0, Df ~0.01 at 1 GHz). BT laminates are commonly used for IC package substrates, BGA substrates, and high-reliability applications where thermal performance exceeds what FR-4 can deliver. The material is more expensive than FR-4 but less costly than polyimide.

### CCL

Copper Clad Laminate (CCL) is the starting material for PCB fabrication - a cured laminate sheet with copper foil bonded to one or both sides. CCL manufacturers (Isola, Rogers, Shengyi, ITEQ, Panasonic) supply materials with specific Dk, Df, Tg, and thermal properties. Quality and consistency of CCL directly affects PCB electrical performance and reliability. Standard FR-4 CCL costs $15-30/m²; high-speed and RF materials can exceed $200/m². Material selection balances electrical requirements, thermal needs, and cost. CCL is cut into panels, imaged, etched, and laminated into multilayer boards.

### ceramic

Ceramic substrates (alumina Al₂O₃, aluminum nitride AlN, LTCC) offer properties unmatched by organic laminates: excellent thermal conductivity (AlN: 170-230 W/mK vs FR-4's 0.3), stable Dk across temperature/frequency, zero moisture absorption, and high-temperature capability. Used for RF/microwave modules, power electronics, and LED packages. Processing differs from PCB - thick/thin film metallization, screen printing, co-fired construction. Cost is 10-100x organic PCBs. Ceramic-filled PTFE (Rogers) provides some ceramic benefits in conventional PCB processing.

### core

A core is a pre-cured laminate sheet with copper foil bonded to both sides - the rigid structural element of a PCB. Cores are manufactured with precise thickness and Dk for impedance control. In multilayer construction, cores are stacked with prepreg (uncured adhesive) between them and laminated under heat and pressure. Core thickness affects impedance, total board thickness, and rigidity. Standard cores range from 0.1mm to 1.6mm. Thinner cores enable tighter impedance control but cost more and are harder to handle. The core's Dk and Df determine electrical performance.

### coverlay

Coverlay is a polyimide film with adhesive backing that's laminated over flex circuit traces as a protective covering, serving the same function as solder mask on rigid PCBs. Unlike photo-imageable solder mask, coverlay is mechanically punched or laser-cut to create openings for pads and vias before lamination. Coverlay is more flexible and durable than liquid solder mask on flex circuits, essential for dynamic flex applications. Typical thickness is 25 µm polyimide plus 25 µm adhesive.

### dielectric

Dielectric refers to the electrically insulating material separating conductive layers in a PCB, including laminate cores and prepreg. Key dielectric properties are dielectric constant (Dk, affecting impedance and signal speed), dissipation factor (Df, affecting signal loss), and dielectric strength (breakdown voltage). Dielectric thickness determines impedance for given trace widths. Materials are selected based on frequency, thermal, and mechanical requirements. Air (Dk=1) is the reference; common PCB dielectrics range from Dk=2.1 (PTFE) to Dk=4.5 (FR-4).

### DuPont

DuPont supplies specialty materials for PCB fabrication. Key products: Pyralux flexible circuit materials (polyimide-based laminates and coverlay), Interra high-Dk laminates for embedded capacitance, and Riston photoresist films. Pyralux is the industry standard for flex circuits - AP (adhesive-based) and LF (adhesiveless) versions. DuPont's Kapton polyimide film is the base for most flex materials. Material specifications and design guides available from DuPont directly. DuPont materials are premium-priced but offer documented performance and consistent supply.

### FaradFlex

FaradFlex is a high-capacitance laminate material manufactured by Oak-Mitsui for embedded capacitance applications. It features thin, high-Dk dielectric (typically 12-24 µm with Dk ~8-16) between copper planes, providing capacitance densities of 0.5-4 nF/cm². FaradFlex layers are laminated into the stackup between power and ground planes, creating distributed capacitance for power supply decoupling. This reduces or eliminates discrete decoupling capacitors at high frequencies where surface-mount caps become ineffective.

### flux

Flux removes oxides from metal surfaces and promotes solder wetting. Types: rosin-based (traditional, leaves residue), no-clean (low residue, most common), water-soluble (aggressive, requires cleaning). Flux in solder paste activates during reflow's preheat/soak phase. Too little flux causes poor wetting; too much causes residue problems. No-clean flux residue is designed to be benign but can cause problems under conformal coating or in high-humidity environments. Water-soluble flux requires thorough cleaning to prevent corrosion. Flux classification (ROL0, REL1, ORH1) indicates activity level and residue type.

### FR-4

FR-4 (Flame Retardant 4) is the most common PCB laminate material, consisting of woven fiberglass cloth impregnated with epoxy resin. Standard FR-4 has a glass transition temperature (Tg) of 130-140°C, dielectric constant (Dk) of 4.2-4.5, and dissipation factor (Df) of 0.02. High-Tg versions (170-180°C) are used for lead-free assembly. FR-4 is cost-effective but has limitations for high-frequency (>3 GHz) and high-reliability applications due to higher losses and moisture absorption.

### FR408

Isola FR408 and FR408HR are high-Tg laminates with lower Dk/Df than standard high-Tg FR-4, bridging the gap between commodity FR-4 and premium low-loss materials. FR408 offers Dk 3.66, Df 0.012, Tg 180°C, and Td 360°C. FR408HR improves further to Dk 3.65, Df 0.0095, and Tg 190°C. Both provide T260 exceeding 60 minutes for robust lead-free processing. The lower Dk (vs. 4.0+ for standard high-Tg) means narrower traces for 50Ω impedance, potentially saving a layer. Choose FR408/FR408HR for 10 Gbps designs where Megtron would be overkill but standard FR-4 causes marginal eye diagrams. Cost positions between standard high-Tg and Megtron 4.

### glass style

Glass style refers to the standardized fiberglass cloth weave patterns used in PCB laminates and prepregs. Common styles include 1080 (light, thin), 2116 (medium, most common), and 7628 (heavy, thick). The number indicates weave density and yarn configuration. Glass style affects dielectric thickness, resin content, and Dk variation (weave pattern causes periodic Dk changes that can affect high-speed signals). Spread glass technology flattens fibers for more uniform Dk. Multiple plies of different glass styles can achieve target thickness.

### halogen-free

Halogen-free PCB materials contain minimal levels of chlorine, bromine, and other halogens, using alternative flame retardants. Halogens are restricted due to environmental concerns: when burned, halogenated materials can release toxic dioxins and furans. Halogen-free is defined by IEC 61249-2-21 as <900ppm chlorine, <900ppm bromine, and <1500ppm total halogens. Halogen-free laminates use phosphorus-based or nitrogen-based flame retardants. Many manufacturers offer halogen-free versions of standard materials (e.g., Isola 370HR is halogen-free).

### high-Tg

Specify high-Tg laminate (Tg ≥170°C) when: your board uses lead-free assembly (required - standard FR-4 fails at 260°C reflow), the board will see more than 3 reflow cycles (rework, double-sided assembly), operating temperature exceeds 105°C, or you need IPC Class 3 reliability. High-Tg materials like IS410, 370HR, and FR408 cost 10-20% more than standard FR-4 but prevent via barrel cracking and delamination under thermal stress. For most lead-free commercial products, high-Tg is now standard practice.

### HVLP

HVLP (Hyper Very Low Profile) copper foil has surface roughness below 2 µm Rz, critical for high-speed signal integrity above 25 Gbps. At high frequencies, current flows near the conductor surface (skin effect), so rough copper increases resistance and signal loss. Standard copper (HTE/STD) has 5-10 µm Rz roughness. RTF (Reverse Treat Foil) provides 3-5 µm Rz for 10-25 Gbps. VLP offers 1.5-3 µm Rz for 25-56 Gbps. HVLP/H-VLP at <2 µm suits 56 Gbps+. HVLP3 achieves ≤1.1 µm Rz for 100 Gbps+ designs. Smoother foil reduces adhesion to laminate, so peel strength and reliability need verification. Specify HVLP copper with Megtron 7/8 or Tachyon 100G for extreme-speed designs.

### hydrocarbon ceramic

Hydrocarbon ceramic laminates (Rogers RO4000 series) combine ceramic filler with hydrocarbon resin and woven glass reinforcement. Benefits: stable Dk (3.38-3.66), low loss (Df 0.0027-0.004), and standard FR-4 processing (no PTFE handling issues). RO4003C and RO4350B are workhorses for commercial RF through 10GHz. Cost is 3-5x FR-4 but far less than pure PTFE. Can be laminated with FR-4 in hybrid stackups. The woven glass enables standard drilling and plating. Widely used in cellular base stations, automotive radar, and commercial wireless.

### I-Tera MT40

I-Tera MT40 is Isola's primary low-loss material for high-speed digital applications. Key specs: Dk 3.45 at 10 GHz (stable from -55°C to +125°C), Df 0.0031 (consistent across 2-10 GHz), Tg 215°C, and Td 360°C. Both T260 and T288 exceed 60 minutes, making it robust for lead-free assembly. I-Tera MT40 works with HVLP copper foils and requires no special through-hole processing unlike PTFE. It competes directly with Megtron 6 for 25-56 Gbps designs. Choose I-Tera MT40 when you need stable Dk across temperature extremes or when your fabricator stocks Isola rather than Panasonic materials.

### Isola

Isola is a major manufacturer of copper-clad laminates and prepregs. Their products include IS400 series (standard and high-Tg FR-4), 370HR (high-reliability FR-4), I-Tera MT40 (low-loss for high-speed digital), and Astra MT77 (ultra-low-loss thermoset). Isola materials are widely used in commercial, automotive, and telecommunications applications. They offer comprehensive Dk and stackup documentation useful for impedance calculations.

### ITEQ

ITEQ Corporation (Taiwan) manufactures laminates from standard FR-4 through advanced high-speed grades. IT-180A is their high-Tg FR-4 (Tg ≥175°C, Td ≥340°C). IT-968 series (IT-968/IT-968BS/IT-968TC) offers Dk <3.8, Df <0.005 for 5G infrastructure and automotive radar. IT-988G achieves Dk <3.63, Df <0.0029 stable across 1-20 GHz, optimized for 56 Gbps+ PAM4 with excellent performance at 14 GHz and 28 GHz Nyquist frequencies. ITEQ has strong halogen-free options across the range. Materials are widely available at Asian fabricators and increasingly at Western shops. ITEQ offers a cost-effective alternative to Isola and Panasonic for high-speed applications.

### Kapton

Kapton is DuPont's trade name for polyimide film, the dominant base material for flexible circuits. Properties: excellent thermal stability (-269°C to +400°C), high dielectric strength, good chemical resistance, and inherent flexibility. Standard thickness is 25µm (1 mil) or 50µm (2 mil). Kapton's amber color is distinctive. Alternatives exist (Apical, Upilex) but Kapton remains the reference. Kapton HN is general purpose; Kapton FN has fluoropolymer coating for better adhesion. Cost is significantly higher than FR-4. Used in flex circuits, aerospace, and high-temperature applications.

### Kingboard

Kingboard Holdings (Hong Kong) is the world's largest CCL manufacturer, controlling significant global market share. Their product line spans standard FR-4 (KB-6160 at Tg 130-145°C) through high-Tg grades (KB-6164 at Tg 150-155°C). Kingboard materials dominate high-volume Asian production due to competitive pricing and broad availability. While Kingboard focuses primarily on standard and mid-performance grades rather than ultra-low-loss materials, their high-Tg products meet lead-free assembly requirements. Most Asian fabricators stock Kingboard as their default FR-4 supplier. For commodity high-volume production, Kingboard offers the best combination of availability, consistency, and cost.

### laminate

Laminate is the fully cured (C-stage) base material of a PCB, consisting of reinforcement (typically fiberglass) and resin, clad with copper foil on one or both sides. Laminates are specified by material type (FR-4, high-frequency, polyimide), thickness, copper weight, and electrical properties (Dk, Df, Tg). In multilayer PCBs, laminates form the cores that are bonded together with prepreg during lamination. The laminate material system must be compatible across all layers.

### Megtron

Megtron is Panasonic's family of low-loss laminates that have become the industry standard for high-speed digital designs. Megtron 4 (Dk 3.8, Df 0.005) handles 5-10 Gbps and costs about 1.5-2x FR-4. Megtron 6 (Dk 3.4 at 10 GHz, Df 0.003-0.004) dominates 10-25 Gbps applications including 5G infrastructure and high-speed networking, at roughly 3-4x FR-4 cost. Megtron 7 (Df 0.003 at 12 GHz) targets 25-56 Gbps with 30% lower loss than Megtron 6. Megtron 8 achieves industry-leading Df of 0.0012 at 10 GHz for 56-112 Gbps PAM4 and 800GbE. Unlike PTFE materials, Megtron processes like standard FR-4 and works in hybrid stackups. Specify Megtron 6 as your baseline for anything above 10 Gbps.

### Ohmega-Ply

Ohmega-Ply is a nickel-phosphorus (NiP) or nickel-chromium (NiCr) resistive film bonded to copper foil, manufactured by Ohmega Technologies. It's laminated into the PCB stackup, then the copper is etched to define resistor shapes while the resistive layer provides the resistance. Available in sheet resistivities from 25Ω/sq to 250Ω/sq, Ohmega-Ply enables tolerances of ±5-10% with laser trimming, suitable for precision applications. The thin-film technology offers better TCR (temperature coefficient of resistance) than thick-film carbon alternatives.

### polyimide

Polyimide (PI) is a high-performance polymer with excellent thermal stability (continuous use to 260°C), chemical resistance, and mechanical flexibility. In PCBs, it's used as the base film for flexible circuits (Kapton is DuPont's brand), high-temperature rigid laminates, and coverlay material. Polyimide has higher moisture absorption than FR-4, which can affect electrical properties and requires bake-out before soldering. Its excellent dimensional stability and high Tg make it preferred for aerospace, military, and implantable medical devices.

### prepreg

Prepreg (pre-impregnated) is fiberglass cloth impregnated with partially cured epoxy resin. B-stage means the resin is solid at room temperature but will flow and complete curing under heat and pressure during lamination, bonding copper layers and cores together. Prepreg is specified by glass style (1080, 2116, 7628) and resin content, which determine cured thickness and dielectric properties. Multiple prepreg sheets can be stacked to achieve target dielectric thickness. Prepreg Dk and thickness are critical for impedance control, so always confirm your fabricator's available prepreg options when designing controlled-impedance stackups.

### PTFE

Polytetrafluoroethylene (PTFE), commonly known by the brand name Teflon, is a fluoropolymer with exceptional electrical properties. PTFE-based laminates have very low dielectric constant (Dk ~2.1) and dissipation factor (Df <0.001), making them ideal for RF and microwave applications above 10 GHz. However, PTFE is difficult to process: it requires special surface preparation (sodium naphthalene or plasma treatment) for copper adhesion, doesn't bond well with standard FR-4 prepregs, and has high Z-axis CTE.

### Pyralux

DuPont Pyralux is the dominant material family for flexible circuits, built on Kapton polyimide film. Pyralux AP (adhesiveless all-polyimide) bonds polyimide directly to copper without adhesive for the best controlled impedance and thermal performance, with Tg ~340°C and Dk ~3.4. Pyralux LF (acrylic-based) has 35+ years of proven reliability. Pyralux HT handles operating temperatures >225°C for EV power modules. Pyralux TK combines FEP fluoropolymer with Kapton for Dk <3.0 in high-frequency flex applications. Standard dielectric thicknesses run 0.5-6.0 mils (7.0-20 mils special order). Specify Pyralux AP for multilayer flex and rigid-flex requiring controlled impedance. Pyralux complies with IPC-4204/11.

### RCC

Resin Coated Copper (RCC) is copper foil with a thin layer of resin on one side, used in HDI build-up processes. RCC is laminated resin-side down onto the panel, creating a dielectric layer with copper ready for patterning. The thin, glass-free resin layer (typically 40-80 µm) enables small laser-drilled micro-vias. RCC simplifies the build-up process compared to using separate prepreg and foil. The resin composition affects dielectric properties and laser drilling characteristics.

### RF-35

Taconic RF-35 uses ORCER (organic ceramic) construction combining ceramic filling with PTFE-coated fiberglass for FR-4-like processing with RF performance. Dk 3.50 ±0.10, Df 0.0019-0.0025, Tg >315°C. The key advantage: RF-35 processes with standard epoxy/glass methods, avoiding sodium naphthalene treatment and special drilling procedures. It's the best choice for low-cost, high-volume commercial microwave production. RF-35TC variant achieves Df 0.0011 with enhanced thermal conductivity and won't oxidize or yellow like some hydrocarbon competitors. Use RF-35 for commercial GPS, WiFi, and cellular applications where RO4350B performance is needed but volume pricing matters.

### RO3003

Rogers RO3003 is a ceramic-filled PTFE laminate with CTE matched to copper (17 ppm/°C X/Y), designed for extreme frequency stability. Dk 3.00 ±0.04 at 10 GHz, Df 0.0010-0.0013, TCDk -3 ppm/°C (exceptional). The copper-matched CTE provides reliability through thermal cycling that pure PTFE cannot match. RO3003 is the standard choice for 77 GHz automotive radar (adaptive cruise control, collision avoidance) and 5G millimeter-wave applications. Like all PTFE materials, it requires surface activation (sodium naphthalene or plasma) for copper adhesion. Cost runs 8-15x FR-4. Specify RO3003 when you need both lowest Df and dimensional stability at millimeter-wave frequencies.

### RO4003C

Rogers RO4003C is a thermoset hydrocarbon ceramic laminate that offers RF performance while processing like FR-4. Dk 3.38 ±0.05 (process) at 10 GHz, Df 0.0027, CTE 11/14/46 ppm/°C, Tg >280°C, thermal conductivity 0.71 W/m·K. Unlike PTFE, RO4003C requires no sodium etch treatment and bonds well with FR-4 in hybrid stackups. It's halogen-free but not UL 94V-0 rated, which may matter for some certifications. Cost runs 2-5x FR-4. Use RO4003C for UHF through X-band (up to ~10 GHz) applications where standard FR-4 loss is unacceptable but PTFE processing is overkill. Common in WiFi, GPS, and cellular front-ends.

### RO4350B

Rogers RO4350B is the most widely used high-frequency laminate globally, offering the best balance of RF performance, processability, and cost. Specs: Dk 3.48 ±0.05 (process) at 10 GHz, Df 0.0037, CTE 14/16/35-41 ppm/°C, Tg >280°C, UL 94 V-0 certified. Frequency stability is demonstrated from 500 MHz to 77 GHz with very low temperature coefficient of Dk. RO4350B processes like FR-4 with no sodium etch required and works well in hybrid stackups with FR-4 for cost optimization. Cost runs 4-6x FR-4 (typically $46-78/sq ft). Default to RO4350B for RF designs from L-band through automotive radar at 77 GHz. Reserve RT/duroid for applications demanding the absolute lowest loss.

### Rogers

Rogers Corporation is a leading manufacturer of high-frequency PCB materials. Their product lines include RO4000 series (thermoset non-PTFE with FR-4 processing), RT/duroid (PTFE/woven glass and ceramic-filled), and TMM (thermoset ceramic-filled). When to choose Rogers: RF designs above 1-2 GHz where FR-4 loss and Dk variation degrade performance, antenna substrates requiring stable Dk, and high-power amplifiers needing thermal conductivity. RO4003C and RO4350B (Dk ~3.38-3.48) are popular up to 10 GHz. For higher frequencies into millimeter-wave, RT/duroid materials are typical. Rogers costs more than FR-4 but most digital designs below 10 Gbps can use standard FR-4 or mid-loss materials.

### RT/duroid 5880

Rogers RT/duroid 5880 is the industry gold standard for lowest-loss RF applications. Dk 2.20 ±0.02 at 10 GHz and Df 0.0009 (the lowest for reinforced PTFE) make it the default for demanding aerospace and satellite systems. Frequency range spans DC to 40+ GHz. The glass-reinforced PTFE construction requires sodium naphthalene treatment or plasma for PTH adhesion. CTE runs 31/48/237 ppm/°C (X/Y/Z), so thermal cycling reliability needs attention. RT/duroid 5880LZ variant achieves Dk 1.96 (lowest available copper-clad laminate) at lower density for weight-critical aerospace. Cost runs 8-15x FR-4. Reserve RT/duroid 5880 for satellite communications, phased arrays, and applications where every 0.001 of Df matters.

### Shengyi

Shengyi Technology is China's largest CCL (copper-clad laminate) manufacturer, offering materials from standard FR-4 to high-speed low-loss grades. S1000/S1000-2/S1000-2M series covers high-Tg FR-4 (Tg 170-180°C) for lead-free assembly. Synamic 6 (S6000) offers Dk 3.50 and Df 0.0046 at 10 GHz for high-speed digital. Synamic 6N achieves Df 0.0026, competing with Megtron 7. Synamic 8GN (S7000) reaches Df ~0.0019 for ultra-low-loss applications. SF305 and SF701 cover flex circuit applications. Shengyi materials are qualified at many Asian fabricators and offer cost advantages over Western brands. Confirm your specific fabricator's Shengyi qualifications before specifying.

### solder paste

Solder paste is powdered solder suspended in flux vehicle, printed through stencils onto SMT pads. Composition: SAC305 (96.5Sn/3Ag/0.5Cu) is standard lead-free; Sn63Pb37 for leaded. Powder size (Type 3, 4, 5) affects print resolution - finer powder for smaller apertures. Paste requires refrigerated storage, limited stencil life (abandon after 8-24 hours). Print quality depends on stencil design, squeegee parameters, and paste condition. Post-print inspection (SPI) catches defects before component placement. Paste volume determines joint reliability.

### spread glass

Spread glass (also called flat glass or mechanically spread glass) refers to fiberglass reinforcement that has been flattened or spread to reduce the periodicity of the weave pattern. Standard glass weaves have alternating regions of glass bundles and resin-rich gaps, creating periodic Dk variation that can affect high-speed signals. Spread glass technology fills more of the openings, providing more uniform Dk across the material. This improves impedance consistency and reduces fiber weave effect, important for very high-speed digital designs.

### Tachyon 100G

Tachyon 100G is Isola's premium ultra-low-loss laminate targeting 100 Gbps and beyond. Dk is exceptionally stable at 3.02-3.04 across 2-10 GHz, and Df reaches 0.0021. Tg of 215°C (DSC) and thermal stability (T260/T288/T300 all exceed 60/60/20 minutes) make it robust for demanding assemblies. The material is compatible with HVLP3 copper foil (≤1.1 µm Rz) for minimum conductor loss at extreme speeds. Available with low-Dk glass, square weave, and mechanically spread glass constructions to minimize fiber weave effect. Performance is validated to 100 GHz. Use Tachyon 100G for backplanes, fine-pitch BGA breakout, and 112 Gbps PAM4 designs where Megtron 7/8 is the alternative.

### Taconic

Taconic is a manufacturer of advanced PCB laminates for RF, microwave, and high-speed digital applications. Their product lines include TLY (low-loss PTFE/woven glass), RF-35 (ceramic-filled PTFE), and TLC (low-cost PTFE). Taconic materials are commonly specified alongside Rogers for high-frequency designs. TLY-5 offers Dk of 2.2 with Df below 0.001, suitable for millimeter-wave applications. Like Rogers PTFE materials, Taconic laminates require special surface preparation for copper adhesion and different processing than FR-4. Choose Taconic or Rogers based on specific Dk, Df, and cost requirements for your frequency range.

### TLY-5

Taconic TLY-5 is a PTFE-based laminate matching RT/duroid 5880's electrical performance at a lower price point for commercial applications. Dk 2.20, Df 0.0009 (matching the lowest reinforced PTFE values). Like all PTFE materials, TLY-5 requires surface treatment for copper adhesion and careful processing for through-hole reliability. Use TLY-5 for commercial satellite, radar, and high-frequency applications where RT/duroid's aerospace heritage isn't required. The lower cost compared to Rogers makes it attractive for volume commercial production. Confirm your fabricator is qualified on TLY-5 specifically, as PTFE processing experience varies.

### TMM

Rogers TMM (Thermoset Microwave Material) series are ceramic-filled hydrocarbon thermosets offering a range of Dk values without PTFE processing requirements. TMM3: Dk 3.27, Df 0.0020. TMM4: Dk 4.50, Df 0.0020. TMM6: Dk 6.00, Df 0.0023. TMM10: Dk 9.20, Df 0.0022. TMM10i: Dk 9.80, Df 0.0020 (can replace alumina substrates). TMM13i: Dk 12.85, Df 0.0019. All have decomposition temperature of 425°C. High-Dk variants enable circuit miniaturization for filters and compact antennas. Unlike PTFE, TMM requires no sodium naphthalene treatment. CTE is well-controlled (15-21 ppm/°C X/Y). Use TMM when you need high Dk for size reduction or want ceramic-like performance without ceramic fabrication complexity.

### Ventec

Ventec International Group manufactures laminates with particular strength in thermal management and halogen-free products. VT-47 is their high-Tg FR-4 (Tg 180°C, Td 355°C, Dk 4.57, Df 0.016) competing with Isola 370HR. The tec-thermal VT-4A series covers metal-core applications: VT-4A1 (1.6 W/m·K), VT-4A2 (2.2 W/m·K), and VT-4BC (10 W/m·K for IGBT and power markets). VT-441/VT-447 offer halogen-free options. Ventec materials are common at European and Asian fabricators. The thermal management focus makes Ventec a natural choice for LED, power electronics, and automotive applications requiring MCPCB construction.

## Manufacturing Processes

Fabrication and assembly techniques

### back-drilling

Back-drilling (also called controlled-depth drilling or stub removal) removes the unused portion of through-hole vias to eliminate via stubs. Stubs act as unterminated transmission line branches, causing resonances and signal reflections at high frequencies. Back-drill depth is controlled to leave a small margin above the target layer. Back-drilling is common for high-speed designs above 5-10 Gbps where stub effects become significant. Alternative technologies include HDI with blind/buried vias to avoid stubs entirely.

### BGA reballing

BGA reballing removes the existing solder balls from a BGA package and attaches new balls, enabling component reuse or repair after removal from a PCB. The process involves cleaning old solder from the BGA pads, applying flux, placing new solder balls (using a stencil or preform), and reflowing to attach them. Reballing is used to salvage expensive components from failed boards, convert BGA ball alloy (leaded to lead-free or vice versa), or restore components after rework attempts. For PCB designers, reballing capability means expensive BGAs (FPGAs, processors) can potentially be recovered if boards fail during bring-up, reducing prototype costs. Not all BGAs are good candidates - moisture-sensitive components may be damaged by multiple reflow cycles.

### boundary scan

Boundary scan (IEEE 1149.1, commonly called JTAG) is a test methodology where ICs include built-in test logic that can control and observe pin states through a serial interface. This enables testing interconnections between chips without physical probe access - essential for fine-pitch BGAs where probe access is impossible. Boundary scan can detect open and short circuits, verify correct component orientation, and even program flash devices. For PCB designers, boundary scan requires: JTAG signals (TCK, TMS, TDI, TDO, optional TRST) routed to a test header, proper termination, and daisy-chain connection between boundary-scan devices. Include JTAG access even on production boards for field diagnostics.

### build-up

Build-up refers to the process of adding layers to a core PCB through sequential lamination, used in HDI construction. Build-up layers are typically thinner than conventional layers and use laser-drilled micro-vias for inter-layer connection. Common build-up materials include RCC (resin-coated copper) and thin prepreg. Build-up layers can be added symmetrically (equal layers each side) or asymmetrically. Each build-up layer requires lamination, laser drilling, and plating cycles, adding to cost and cycle time.

### conformal coating

Conformal coating is a thin protective film applied to assembled PCBs to shield components and circuitry from environmental hazards. Common coating materials include acrylic (easy rework), silicone (wide temperature range), polyurethane (chemical resistance), and epoxy (hard, durable). The coating conforms to board contours at 25-250 µm thickness, protecting against moisture, dust, chemicals, and temperature extremes while providing electrical insulation. Application methods include spraying, dipping, and selective coating. Specify conformal coating for automotive, aerospace, marine, and industrial environments. Design considerations: define keep-out areas for connectors and test points, and note that coated boards are harder to rework.

### copper plating

Copper plating deposits copper onto PCB surfaces through electrochemical reduction. Two types: electroless (chemical reduction, provides initial conductivity on drilled hole walls) and electrolytic (uses applied current, builds up thickness). Standard process adds 20-25µm to hole walls; thicker plating improves reliability but reduces hole diameter. Plating distribution depends on pattern density - isolated features plate thicker than dense areas. Plating thickness affects impedance (thicker traces have lower impedance), current capacity, and via reliability. Quality is verified through microsection measurement.

### depaneling

Depaneling separates individual PCBs from the manufacturing panel after assembly is complete. Methods include V-score break (snap along pre-scored lines), routing (cutting with spinning router bit), punching/die cutting (stamping out boards), and laser cutting (for flex circuits or precision edges). Each method has trade-offs: V-score is fast but limited to straight edges with rough break lines; routing is flexible but slower and creates dust; laser is precise but expensive. For PCB designers, depaneling affects component placement - keep components at least 3mm from V-score lines to avoid stress damage, and 1mm from routed edges. Tall components near breakaway tabs may interfere with depaneling fixtures.

### drilling

Drilling creates holes for vias, through-hole components, and mounting. Mechanical drilling uses carbide or diamond-coated bits spinning at 100,000+ RPM, achieving minimum diameters around 0.15-0.2mm in production. Laser drilling (CO2 or UV) creates micro-vias (0.075-0.15mm) by ablating material layer by layer. Drill registration, positional accuracy, and hole wall quality are critical. Entry and backup materials reduce burrs and improve hole quality. Drill wear affects hole quality in production runs.

### electroless plating

Electroless plating deposits metal through an autocatalytic chemical reduction reaction, without external electrical current. The process provides uniform thickness regardless of geometry (unlike electroplating which varies with current density). Electroless copper is used to make drilled holes conductive before electroplating. Electroless nickel (in ENIG) provides a barrier layer with phosphorus content affecting properties. Electroless processes require precise chemistry control but enable plating on non-conductive substrates and complex geometries.

### electroplating

Electroplating uses electric current to deposit metal ions from solution onto a conductive surface. In PCB fabrication, acid copper electroplating builds up copper thickness on traces and in via holes after electroless copper makes them conductive. Pattern plating deposits copper (then tin as etch resist) only on circuit features; panel plating coppers the entire panel first. Electroplating thickness varies with current density, requiring careful tank design and agitation for uniform deposition in high-aspect-ratio holes.

### etching

Etching removes unwanted copper using chemical solutions (etchants), leaving the protected circuit pattern. Common etchants include cupric chloride and alkaline ammonia. The process is either subtractive (start with full copper, etch away unwanted areas) or semi-additive (start with thin copper, pattern plate, flash etch). Etch factor describes the ratio of vertical to lateral etching; more lateral etch (undercut) limits fine-feature resolution. Spray etching provides better control than immersion. Etchant chemistry affects speed, copper recovery, and environmental impact.

### flip chip

Flip chip mounts a bare die face-down with solder bumps connecting directly to the substrate - no wire bonds. Benefits: shortest possible interconnect (lowest inductance), higher I/O density, better thermal path through the die back. Challenges: requires precise bump placement, underfill for reliability, substrate with matching bump pitch (often 0.15-0.4mm). Used in high-performance processors, RF devices, and space-constrained applications. PCB substrates for flip chip need HDI capability with micro-vias for escape routing from the dense bump array.

### flying probe

Flying probe testing uses motorized probes that move across the PCB to verify electrical connections, testing continuity (opens) and isolation (shorts). Unlike bed-of-nails fixtures, flying probe requires no dedicated tooling, making it economical for prototypes and low/medium volumes. Test time is longer than fixture testing (seconds to minutes per board vs. under a second) but setup is immediate. Modern flying probe testers achieve <25 µm positional accuracy, enabling testing of fine-pitch features. Some systems include capacitive measurement for embedded components.

### functional test

Functional test (FCT) verifies that an assembled PCB operates correctly by powering the board and testing its actual functionality, often simulating real-world operating conditions. Unlike ICT which tests individual components, functional test validates the complete system: firmware execution, communication interfaces, sensor responses, and output signals. Test fixtures connect to the board through production connectors or dedicated test points. For PCB designers, functional test affects: connector placement (accessible for fixture connection), test point provision (for probing internal signals), debug headers (UART, JTAG for diagnostics), and LED/indicator placement (for visual verification). Include test modes in firmware that exercise board functions systematically.

### ICT

In-Circuit Test (ICT) uses a custom fixture with spring-loaded probes (bed-of-nails) that contact test points on the PCB to verify component presence, orientation, and values. ICT can detect missing components, wrong values, shorts, opens, and some functional defects. For PCB designers, ICT requires dedicated test points - typically 0.9-1.0mm pads on a 2.54mm grid, accessible from one side of the board. Provide at least one test point per net for full coverage. ICT fixtures are expensive ($2,000-$15,000) so ICT suits medium-to-high volume production. For prototypes and low volume, flying probe test achieves similar coverage without fixtures.

### immersion gold

Immersion gold is a thin (0.05-0.1 µm) gold layer deposited by a chemical displacement reaction where gold ions replace surface atoms of an underlying metal (usually nickel in ENIG). Unlike electrolytic plating, immersion is self-limiting: deposition stops when the underlying metal is covered. Immersion gold protects the nickel from oxidation and provides a solderable surface. The thin layer dissolves into the solder during reflow, exposing the nickel for intermetallic formation. Immersion gold alone (without nickel) is not used due to gold embrittlement concerns.

### impedance control

Impedance control maintains trace characteristic impedance within specified tolerance - typically ±10%, tighter (±5%) available at premium. Requires: controlled dielectric thickness (prepreg/core selection), trace width accuracy, and consistent Dk. Fabricators measure impedance on test coupons using TDR. Achieving tight impedance tolerance requires specifying stackup details or letting the fabricator design it to your target impedance. Cost premium for controlled impedance: 10-20% over standard fabrication. Essential for high-speed digital (DDR, PCIe, USB) and all RF designs. Request impedance test reports for critical applications.

### lamination

Lamination bonds multiple PCB layers (cores and prepregs) into a solid multilayer structure using heat and pressure in a lamination press. The B-stage resin in prepregs flows and cures, permanently joining the layers. Critical parameters include temperature profile, pressure, and time. Lamination voids, delamination, and resin starvation are common defects. Controlled-depth drilling for buried vias requires lamination of sub-composites before final stack-up. High-layer-count boards may use sequential lamination with multiple press cycles.

### laser drilling

Laser drilling uses focused laser energy to ablate PCB material, creating micro-vias too small for mechanical drills. CO2 lasers (10.6 µm wavelength) ablate dielectric but stop on copper, used with copper-windowed structures. UV lasers (355 nm) can ablate both dielectric and thin copper, enabling blind via formation without pre-etched windows. Laser drilling is faster and more precise than mechanical for small holes but limited to ~150 µm minimum diameter and shallow depths (typically single-layer). Direct laser ablation is used for buried/blind via processing.

### lead-free

Lead-free assembly is required for RoHS compliance and affects your PCB specification. The higher reflow temperatures (peak ~260°C vs ~230°C for leaded) require: high-Tg laminate (Tg ≥170°C), compatible surface finishes (ENIG, immersion silver, OSP, or lead-free HASL), and components rated for lead-free processing. When specifying a lead-free board, confirm your fabricator uses compatible surface finish and your components are MSL-rated for the higher temperatures. Lead-free solder (SAC305 or SAC387) has different wetting characteristics - discuss assembly requirements with your CM.

### microsection

Microsection (or cross-section) is a quality inspection technique where a PCB sample is cut, mounted in epoxy, polished, and examined under microscope. Microsectioning reveals internal features: copper thickness, plating quality, via fill, layer registration, laminate voids, and defects. It's a destructive test, performed on dedicated coupons or sample boards. Microsection analysis is required for IPC qualification, failure analysis, and first-article inspection. High-magnification SEM microsection can reveal nano-scale features and intermetallic compounds.

### panel bars

Panel bars (also called rails, borders, or tooling strips) are the frame around the perimeter of a PCB panel that holds individual boards together during fabrication and assembly. They provide structural support to keep the array rigid through solder paste printing, pick-and-place, and reflow, preventing warping that causes registration issues. This is particularly important for thin boards or designs with large internal cutouts. The bars include space for tooling holes (fixturing), fiducial marks (machine vision alignment), and sometimes test coupons or impedance structures. Conveyor systems grip these rails to transport panels between SMT stations, making adequate width essential for reliable handling. Panel bars also create a buffer zone between edge-mounted components and conveyor mechanisms, allowing components closer to the board edge than on unpanelized boards. For wave or selective soldering, the rails provide mounting points for pallets and fixtures. Individual boards connect via breakaway tabs with mouse bites or V-score lines. Typical width is 5-15mm depending on requirements. Wider bars provide more rigidity and tooling space but reduce panel utilization.

### panelization

Panelization arranges multiple PCB units on a larger manufacturing panel to improve handling efficiency and reduce cost. Units are connected by breakaway tabs (with V-score or routed perforations) or placed in a rail frame. Standard panel sizes are 18×24 inches (457×610mm) or 21×24 inches (533×610mm). Larger panels reduce cost per board but require larger handling equipment. When designing for panelization, account for component overhang at board edges, maintain 3mm clearance from V-score lines to sensitive components, and discuss array layout with your fabricator before finalizing.

### pick and place

Pick and place machines are automated systems that pick SMD components from feeders (reels, trays, tubes) and place them onto solder paste deposits on PCBs. High-speed machines place 20,000-80,000 components per hour for passive and small ICs, while precision placers handle fine-pitch BGAs and QFPs at slower speeds with higher accuracy (±25 µm or better). For PCB designers, pick and place affects: minimum component spacing (typically 0.5mm between bodies for nozzle clearance), fiducial requirements for alignment, component orientation consistency, and panel rail width for conveyor transport. Provide accurate centroid data (X, Y, rotation) in your assembly files.

### plating

Plating deposits metal onto PCB surfaces through electrochemical processes. Electroless plating provides initial conductivity on non-conductive surfaces (drilled hole walls); electroplating builds up copper thickness. Standard plating adds 20-25µm copper to hole walls for reliable interconnection. Thicker plating (35-50µm) improves reliability for thermal cycling. Over-plating causes problems - reduced hole diameter, uneven surfaces. Pattern plating vs panel plating affects final copper thickness and distribution. Plating quality directly affects via reliability and is verified through microsection analysis.

### reflow

Reflow soldering melts solder paste to attach surface-mount components. The process: print paste through stencil, place components, run through reflow oven with controlled temperature profile (preheat, soak, reflow peak, cooling). Lead-free (SAC305) requires peak temperatures of 245-260°C; leaded solder peaks at 210-225°C. Profile matters - too fast causes tombstoning and solder balls; too slow damages components. Double-sided boards need two reflow passes. The thermal mass of the assembly affects profile requirements. Most PCB assemblies use reflow as the primary soldering method.

### reflow oven

A reflow oven heats PCB assemblies through a controlled temperature profile to melt solder paste and form solder joints. Modern ovens use convection heating with multiple zones: preheat (ramp to ~150°C), soak (flux activation), reflow (peak at 235-260°C depending on alloy), and cooling. The thermal profile must balance heating all joints adequately while not exceeding component temperature ratings. For PCB designers, reflow affects: component selection (check MSL ratings for peak temperature), thermal mass balancing (large ground planes heat slower, causing tombstoning), and double-sided assembly sequence (bottom-side components must survive second reflow). Lead-free reflow requires higher temperatures than leaded, stressing components and laminates more.

### reflow soldering

Reflow soldering is the standard process for attaching surface-mount components. Solder paste (flux plus solder powder) is stencil-printed onto pads, components are placed by pick-and-place machine, then the assembly passes through a reflow oven with controlled temperature profile. The profile includes preheat (activate flux, equalize temperature), soak (remove volatiles), reflow (solder melts and wets), and cooling zones. Lead-free reflow requires higher peak temperatures (~260°C vs ~230°C for leaded), stressing components and PCBs.

### rework station

Rework stations are specialized tools for removing and replacing SMD components on assembled PCBs. Hot air stations use focused heated air to reflow solder on specific components. BGA rework stations add bottom-side heating (to prevent board warpage), optical alignment systems, and controlled placement. IR stations use infrared heating for larger areas. For PCB designers, rework considerations include: component accessibility (space around BGAs for nozzle access), thermal isolation (nearby heat-sensitive components may be damaged), and pad design (pads must survive multiple reflow cycles). Designing for reworkability matters for prototypes, high-value boards, and products requiring field repair. Some designs intentionally sacrifice reworkability for density.

### screen printer

A screen printer (or stencil printer) deposits solder paste onto PCB pads by forcing paste through stencil apertures using a squeegee blade. The machine aligns the stencil to the PCB using fiducials, lowers the stencil onto the board, sweeps paste across with controlled pressure and speed, then separates cleanly. Print quality depends on stencil design, paste rheology, squeegee parameters, and separation speed. For PCB designers, screen printing affects: fiducial placement and design (required for alignment), pad design (affects paste release), and solder mask design (mask near pads can interfere with stencil gasketing). Consistent pad sizes within a design improve print quality across the board.

### selective soldering

Selective soldering applies solder to specific through-hole locations rather than the entire board bottom, enabling through-hole assembly on boards with SMT components on the solder side. A programmable nozzle or mini-wave applies molten solder only where needed. This is essential for mixed-technology boards where wave soldering would damage bottom-side SMT components. For PCB designers, selective soldering affects layout: provide 2-3mm clearance around through-hole pins for nozzle access, use thermal relief on through-hole pads connected to planes, and group through-hole components to minimize soldering time. Selective soldering costs more per joint than wave soldering but enables designs that combine SMT density with through-hole connector strength.

### sequential lamination

Sequential lamination involves multiple press cycles to build up a PCB, enabling buried vias and complex HDI structures. First, inner sub-composites are fabricated with their own vias and circuits. These are then laminated together with additional prepreg and foil, followed by outer layer processing. Each cycle adds cost and time but enables structures impossible with single lamination. High-layer-count boards may require 3-4 lamination sequences. Process control of registration and z-axis expansion is critical.

### SMT

Surface Mount Technology (SMT) is the assembly process for mounting SMD components using automated placement and reflow soldering. For PCB designers, SMT-compatible design means: pads sized per IPC-7351, consistent pad orientation for wave or selective soldering if mixed with through-hole, thermal relief on pads connected to planes (prevents tombstoning from uneven heating), and adequate spacing for pick-and-place nozzles (typically 0.5mm between component bodies). Fiducial marks on the PCB help machine vision align placement. Design for double-sided SMT requires consideration of which side reflows first.

### solder bridge

A solder bridge is an unintended solder connection between two or more pads or traces that should be electrically isolated. Bridges cause short circuits that can damage components or prevent the board from functioning. Common causes include excessive solder paste, insufficient pad spacing, poor stencil design, or component misalignment. PCB design prevention: maintain adequate pad-to-pad spacing (minimum 0.2mm for fine-pitch, 0.3mm preferred), use solder mask dams between pads where possible, and follow IPC footprint recommendations. Solder bridges are detected by AOI or electrical testing and can often be repaired by reflow or manual touch-up.

### solder joint

A solder joint is the metallurgical connection between a component terminal and a PCB pad. Joint reliability depends on: alloy choice (SAC305 for lead-free, Sn63Pb37 for leaded), pad design (size, finish), thermal profile, and mechanical stress. Good joints show smooth, shiny fillets with proper wetting. Defects include cold joints (insufficient heat), tombstoning (uneven heating), bridging (excess solder), and voids (trapped gas). Thermal cycling causes fatigue - larger joints with proper fillet geometry last longer. X-ray inspection reveals internal voids in BGA joints.

### SPI

Solder Paste Inspection (SPI) systems measure solder paste deposits immediately after stencil printing and before component placement. Using laser or structured light, SPI measures paste volume, height, area, and position for each pad. Catching paste defects early prevents downstream assembly failures - insufficient paste causes open joints, excess paste causes bridges, and offset deposits cause tombstoning. SPI has become standard in quality-focused assembly lines because paste printing accounts for 60-70% of SMT defects. For designers, SPI capability means your assembly house can verify that fine-pitch pads receive adequate paste, enabling confident use of 0.4mm pitch components.

### stencil

A stencil is a thin stainless steel sheet (typically 100-150 µm thick) with laser-cut apertures that align with PCB pads. During SMT assembly, the stencil is placed over the board and solder paste is squeegeed across, depositing paste only where apertures exist. Stencil thickness and aperture size control paste volume. Thinner stencils (100 µm) suit fine-pitch components; thicker stencils (150 µm) provide more paste for larger components. For mixed designs, step stencils have different thicknesses in different areas. Aperture design follows area ratio rules: aperture area ÷ wall area should exceed 0.66 for reliable paste release.

### surface finish

Surface finish protects exposed copper pads and holes from oxidation while providing a solderable surface. Common options: HASL (hot air solder leveling) is cheapest but has uneven surface; ENIG (electroless nickel/immersion gold) provides flat surface for fine-pitch; OSP (organic solderability preservative) is low-cost but short shelf life; immersion silver and immersion tin offer alternatives. Choice affects solderability, shelf life, wire bondability, contact resistance, and cost. ENIG is the default for fine-pitch BGAs; HASL works for standard through-hole and larger SMT.

### test coupon

Test coupons are dedicated structures that replicate production board features for quality verification without destructive testing of product boards. Impedance coupons contain transmission line structures (same layer, trace width, and stackup as the product) with probe launch pads for TDR measurement - typically 100-150 mm trace length for clean readings. Microsection coupons are cross-sectioned to verify plating thickness, hole quality, and registration. Coupons are usually placed in panel margins (same process conditions as product, discarded at depaneling), as breakaway tabs (stays with board until customer removes), or on separate test panels (retained by fabricator as batch records). Standard practice: fabricator measures, logs results, and provides a test report; physical coupons delivered only on request for incoming QC or audit purposes.

### test harness

A test harness is a custom fixture that interfaces between test equipment and a PCB under test, providing mechanical support and electrical connections for automated testing. Bed-of-nails fixtures use spring-loaded pogo pins that contact test points when the board is pressed down. Cable harnesses connect through production connectors for functional testing. Vacuum fixtures hold boards in position during high-speed testing. For PCB designers, test harness requirements affect layout: provide accessible test points (typically 0.9-1mm pads) on a regular grid where possible, ensure adequate clearance for pogo pins (1.9mm minimum between points), place test points on one side only for single-sided fixtures, and use production connectors that can handle repeated mating cycles. Discuss test strategy with your CM early - fixture design often drives test point placement.

### thermal profile

A thermal profile defines the temperature that a PCB assembly experiences through a reflow oven over time. Key zones: preheat (ramp rate <3°C/s to avoid thermal shock), soak (flux activation, typically 150-200°C for 60-120s), reflow (above liquidus, 30-60s above 217°C for SAC305), and cooling (controlled rate to avoid brittle joints). Profile depends on solder paste, component thermal mass, and board size. Too hot damages components; too cool causes poor wetting. Thermocouples on the actual assembly verify the profile. Lead-free requires higher peak temperatures than leaded.

### tombstoning

Tombstoning occurs when a small two-terminal component (typically 0402 or 0603 chip resistor/capacitor) stands up on one end during reflow soldering. The defect happens when solder on one pad melts before the other, and surface tension pulls the component vertical. Causes include unequal pad sizes, unbalanced thermal mass (one pad connected to a large copper pour), asymmetric paste deposits, or component placement offset. PCB design mitigations: use identical pad geometry on both ends, add thermal relief to pads connected to planes, and ensure symmetric routing. Tombstoning is more common with lead-free solder due to higher surface tension.

### tooling

Tooling encompasses the fixtures and setups required for PCB fabrication and assembly. Fabrication tooling: drill files, imaging tools, routing programs, electrical test fixtures. Assembly tooling: solder paste stencils, pick-and-place programs, selective solder fixtures, test jigs. NRE (non-recurring engineering) covers tooling costs - stencils ($100-300), test fixtures ($500-5000), custom fixtures more. First-article builds verify tooling before production. Changes require tooling updates. Design for standard tooling (panel sizes, test point access) reduces costs. Tooling amortizes over production volume.

### underfill

Underfill is an epoxy material dispensed under BGA, CSP, and flip chip packages after soldering, then cured to form a solid bond between the component and PCB. The underfill mechanically couples the component to the board, distributing thermal expansion stress across the entire interface rather than concentrating it at solder joints. This dramatically improves reliability under thermal cycling - critical for automotive, aerospace, and portable electronics that experience repeated temperature swings. For PCB designers, underfill-compatible designs need adequate clearance around BGAs for dispensing (typically 0.5-1mm), and via-in-pad should use filled/capped vias to prevent underfill wicking into holes.

### V-score

V-scoring cuts partial-depth grooves (typically 1/3 depth from each side) along panel separation lines, allowing individual PCBs to be snapped apart after assembly. V-scoring is faster and lower-cost than routing but limits board shape to straight lines, creates stress during depaneling (keep components 3mm from score line), and leaves rough edges. Score depth affects break-out force and edge quality. V-scoring works best for rectangular boards without components near edges. Tab-routing is preferred for irregular shapes or sensitive assemblies.

### wave soldering

Wave soldering is used primarily for through-hole component attachment. The PCB passes over a wave or fountain of molten solder that contacts the bottom side, wetting exposed pads and component leads. Selective wave soldering uses masks or nozzles to solder only specific areas. Wave soldering is less common as SMT dominates, but remains important for connectors, transformers, and other through-hole parts. Mixed-assembly boards may use wave soldering after SMT reflow, requiring careful thermal management.

### X-ray inspection

X-ray inspection uses X-ray imaging to examine solder joints that are hidden from optical inspection, particularly under BGA, QFN, and LGA packages where joints are beneath the component body. X-ray reveals voids in solder joints (acceptable up to 25% for most applications), head-in-pillow defects, bridging between BGA balls, and incomplete joints under QFN thermal pads. Automated X-ray inspection (AXI) systems provide 2D or 3D tomographic imaging for production inspection. For PCB designers, X-ray inspection capability means BGAs and QFNs can be used confidently - the hidden joints are verifiable. Specify X-ray inspection in your assembly requirements for boards with hidden-joint components.

## PCB Features & Components

Physical features, vias, pads, and structures

### annular ring

The annular ring is the copper area between the edge of a drilled hole and the edge of the copper pad. Adequate annular ring prevents pad lift-off during assembly, ensures reliable solder joints, and survives thermal cycling without cracking. IPC standards specify minimum annular ring based on class: 50 µm for Class 2 (general electronics), 75 µm for Class 3 (high reliability). Insufficient annular ring causes intermittent connections and field failures. HDI designs with micro-vias can use smaller annular rings due to better laser drilling accuracy.

### antenna

PCB antennas integrate radiating elements directly on the board - patch antennas, IFAs (inverted-F), PIFAs, meander lines, or chip antenna feeds. Benefits: no external antenna cost, smaller form factor, reproducible performance. Design factors: substrate Dk affects antenna size (higher Dk = smaller), ground plane size affects gain, clearance keep-outs are critical. Simulated with EM tools (HFSS, CST). Common for WiFi, Bluetooth, cellular, GPS, and NFC. Antenna performance is highly sensitive to nearby components, enclosure, and user interaction. Prototype validation essential.

### blind via

A blind via connects an outer layer to one or more inner layers but does not go through the entire board thickness. Blind vias are created by controlled-depth drilling (mechanical or laser) or by drilling the sub-composite before lamination. They save routing space by allowing traces on inner layers beneath the via. Blind vias are more expensive than through-hole vias and require careful process control for depth accuracy. Common in HDI designs, they're designated by layer range (e.g., 1-2 for L1 to L2).

### broadside-coupled differential pair

Broadside-coupled differential pairs stack one trace directly above its pair mate on adjacent signal layers, rather than placing them side-by-side. This enables high-density routing through BGA fanouts and single-track-width routing where horizontal space is limited. However, this apparently simple construction is actually one of the most difficult to fabricate with consistent impedance results. Layer-to-layer registration tolerances and etch differences between the two signal layers both affect coupling symmetry. Broadside coupling is used in USB Type-C designs where pairs must cross over and in tight BGA breakout routing.

### buried via

A buried via connects two or more inner layers without reaching either outer surface of the PCB. Buried vias are created by drilling and plating the sub-composite (core or build-up layers) before final lamination. They maximize routing density by allowing connections that don't consume space on outer layers. Buried vias increase manufacturing complexity and cost, as each buried via layer requires separate drilling and plating operations. Commonly used in high-layer-count boards where through-hole vias would waste routing channels.

### castellated holes

Castellated holes (also called castellations or half-holes) are plated through-holes cut in half at the board edge, creating semi-circular pads along the edge. They're used to attach modular sub-assemblies (like wireless modules) to a host PCB by soldering the castellation to pads on the carrier board. Manufacturing requires drilling, plating, then routing through the hole center to create the half-cylinder shape. Castellation pitch is typically 1.27mm or 2.54mm. The plated surface allows visual inspection of solder joints.

### coated microstrip

Coated microstrip is surface microstrip with solder mask covering the trace - the realistic condition for most production PCBs. The coating typically lowers impedance by 2-3 ohms depending on mask type, thickness, and coverage pattern. For differential pairs, solder mask can flood into the gap between traces, significantly affecting coupling and impedance. Field solvers like Polar Si8000m model coating thickness both above and beside traces. Always specify coated microstrip (not bare surface microstrip) when calculating impedance for production boards with solder mask.

### coplanar waveguide

Coplanar waveguide (CPW) is a transmission line structure where a signal trace is flanked by ground conductors on the same layer, with or without a ground plane below (grounded CPW, GCPW). CPW offers easy integration with surface-mount components since signal and ground are on the same surface. Impedance is controlled by the trace width and gaps to the coplanar grounds. GCPW provides better shielding and tighter impedance control. CPW transitions are common for RF probe testing and connector launches.

### crosshatch ground plane

Crosshatch (or mesh) ground planes use a pattern of copper lines instead of solid copper fill to improve mechanical flexibility in flex and rigid-flex circuits. The hatch pattern is defined by hatch pitch (HP), hatch width (HW), and percentage copper area. Without proper modeling, crosshatch planes significantly alter impedance versus solid-plane calculations - the reduced copper coverage increases the effective distance to the reference plane. Crosshatch is also used in interposer boards and designs requiring manufacturable trace widths on very thin substrates where solid planes would require impossibly narrow traces.

### differential coplanar waveguide

Differential coplanar waveguide routes two central signal traces alongside each other, surrounded by ground conductors on the same layer, with optional ground plane below. This creates a ground-signal-signal-ground (GSSG) configuration that provides both differential signaling benefits (noise rejection, EMI reduction) and coplanar isolation advantages (same-layer return path, RF performance). The structure is used in high-speed and RF applications where both differential signaling and controlled impedance at high frequencies are required.

### differential pair

A differential pair consists of two traces carrying complementary signals (equal magnitude, opposite polarity). The receiver responds to the voltage difference between the two traces, rejecting common-mode noise that affects both equally. Differential signaling is standard for high-speed interfaces (USB, HDMI, Ethernet, PCIe). Critical design parameters include differential impedance (typically 90-100Ω), intra-pair spacing, length matching (skew <10% of bit period), and maintaining constant spacing through the route.

### dual stripline

Dual stripline places two signal layers sandwiched between outer reference ground planes, with the two routing layers typically oriented orthogonally (90 degrees to each other) to minimize interlayer crosstalk. This high-density configuration effectively creates two offset striplines sharing the same outer ground planes. The orthogonal routing prevents long parallel runs that would couple signals between the two signal layers. Dual stripline is common in designs where routing density is critical and layer count must be minimized.

### edge plating

Edge plating applies copper plating to the routed or scored edges of a PCB, creating a continuous conductive surface for grounding, EMI shielding, or edge card connections. The process requires routing or scoring the board edges before copper plating, then final routing to size. Edge plating connects to ground planes on inner layers, providing a low-inductance path for EMI shielding. It's also used for wraparound grounding on RF modules and for edge-launched RF connectors.

### edge-coupled differential pair

Edge-coupled differential pairs place two signal traces side-by-side on the same layer with controlled gap spacing. The electromagnetic coupling between traces carries the differential signal while providing common-mode noise rejection. Impedance is characterized by odd-mode (Zodd) and even-mode (Zeven) values, with differential impedance approximately 2x Zodd. Standard targets include 90 ohms (USB, HDMI), 85 ohms (PCIe, SATA), and 100 ohms (Ethernet). Edge coupling is the most common differential configuration due to simple manufacturing and easy access for testing.

### embedded microstrip

Embedded microstrip is a signal trace buried within the PCB dielectric, referenced to a single plane below but with additional dielectric material above (not a second reference plane - that would be stripline). Embedding lowers impedance by approximately 20% compared to equivalent surface microstrip due to the increased effective dielectric constant. Embedded microstrip offers better EMI containment than surface traces since the dielectric above provides some shielding, while still allowing access from one side for test points if needed.

### fiducial

Fiducials are copper marks on a PCB that provide reference points for automated assembly equipment. Pick-and-place machines use camera systems to locate fiducials and calculate the precise position and rotation of the board or panel. Global fiducials (typically 3 per panel, in an L-pattern) align the entire panel, while local fiducials near fine-pitch components (BGAs, QFPs <0.5mm pitch) improve placement accuracy for those specific parts. Standard fiducial design: 1mm diameter copper circle with 2mm solder mask opening, no silkscreen. Place fiducials on the same layer as the components they reference. Asymmetric placement prevents 180° orientation errors.

### GCPW

Grounded coplanar waveguide (GCPW), also called conductor-backed coplanar waveguide (CBCPW), combines coplanar ground isolation with traditional ground-plane referencing. A signal trace is flanked by ground conductors on the same layer (ground-signal-ground), with an additional ground plane on the opposite side of the substrate. GCPW extends the usable frequency range of FR-4 because most of the field travels between the trace and coplanar grounds through air rather than the lossy laminate. For flex circuits, GCPW keeps return paths on the same layer as signals, avoiding a stiff mechanical I-beam structure that resists bending.

### ground plane

A ground plane is a continuous copper layer connected to system ground, serving as current return path, voltage reference, and electromagnetic shield. Ground planes are essential for controlled impedance (providing the reference for microstrip and stripline), signal return currents (which flow beneath their traces), and EMI containment. Plane splits and voids can cause signal integrity problems by disrupting return current flow. Good practice places ground planes adjacent to signal layers and avoids routing signals over plane gaps.

### micro-via

A micro-via is a small-diameter via (typically 75-150 µm) created by laser drilling rather than mechanical drilling. Micro-vias connect adjacent layers in HDI stackups, enabling high-density routing for fine-pitch BGAs. They have lower inductance and capacitance than through-hole vias, improving signal integrity. Micro-vias can be stacked (directly on top of each other) or staggered, with stacked vias requiring copper filling for reliability. Aspect ratio is typically limited to 0.75:1 to 1:1.

### microstrip

Microstrip is a transmission line structure where a signal trace runs on an outer PCB layer with a ground or power plane as the reference below. Because part of the electromagnetic field travels through air (Dk=1) and part through the laminate, microstrip calculations use an effective dielectric constant lower than the laminate's rated Dk. For FR-4 with Dk of 4.3, effective Dk is typically around 3.3-3.5 depending on geometry. Microstrip is easy to probe and test but is more susceptible to crosstalk and EMI than stripline. Use stripline for sensitive signals that need better shielding.

### multilayer

A multilayer PCB has three or more copper layers laminated together with insulating dielectric material. The innermost layers are etched cores; outer layers start as copper foil. Connections between layers are made with plated through-holes, blind vias, and buried vias. Multilayer construction enables complex routing, dedicated power/ground planes, and controlled impedance. Layer stackup design balances signal integrity, manufacturability, and cost. Most complex electronics use 4-16 layer boards; extreme applications may use 30-50+ layers.

### offset stripline

Offset stripline (also called asymmetric stripline) is a signal trace sandwiched between two reference planes but positioned closer to one plane than the other. This is the realistic representation of most stripline routing since PCB stackups rarely place traces at the true center between planes. The asymmetry means different dielectric thicknesses (H1 and H2) above and below the trace, and often different dielectric constants since one side is typically core material and the other prepreg. Field solvers account for this asymmetry when calculating impedance.

### pad

A pad is a copper area designed for component attachment (SMT or through-hole) or via termination. SMT pads match component footprints with size optimized for solder joint reliability. Through-hole pads include an annular ring around the drill hole. Pad size affects soldering: too small causes insufficient joints, too large wastes space and can cause bridging. Pad shape can be round, square, oblong, or custom. Thermal relief connects pads to planes while maintaining solderability. Pad-to-pad clearance must meet design rules. Non-plated pads serve as test points or mounting features.

### power plane

A power plane is a copper layer dedicated to distributing power supply voltage(s) across the PCB. Power planes form part of the power distribution network (PDN) along with decoupling capacitors. Multiple voltage domains may share a plane with splits or isolated pours. Power planes also serve as reference planes for adjacent signal layers if continuous enough. Effective PDN design minimizes impedance from power supply to component power pins across all frequencies. Plane capacitance (distributed capacitance between power and ground planes) provides high-frequency decoupling.

### QFN

Quad Flat No-lead (QFN) is a leadless surface-mount package with contact pads on the bottom perimeter and typically an exposed thermal pad in the center. QFNs offer smaller size, better thermal performance, and lower inductance than leaded packages like QFP. The exposed pad requires via-in-pad or closely spaced thermal vias for heat transfer to inner layers. QFN assembly requires careful stencil design to avoid voids under the thermal pad that cause overheating. Standard pitches are 0.5mm and 0.65mm.

### silkscreen

Silkscreen (or legend) is the printed marking layer on PCB surfaces showing component reference designators, polarity marks, pin 1 indicators, logos, and other text. Traditionally applied by screen printing with white epoxy ink, modern processes use inkjet printing for finer resolution. Silkscreen aids assembly and debugging but adds cost. Minimum line width is typically 0.15mm (6 mil), with 0.2mm (8 mil) for better readability. Silkscreen should not overlap pads or vias.

### SMD

Surface Mount Device (SMD) is any component mounted on PCB surface pads rather than through holes. SMD packages include passives (0201, 0402, 0603), ICs (SOIC, QFP, QFN, BGA), and connectors. For PCB design, SMD requires precise pad geometry per IPC-7351 footprints, copper-defined or solder-mask-defined pad styles, and thermal relief connections to planes. Choose SMD over through-hole when: board space is limited, automated assembly is planned, or high-frequency performance matters (shorter leads = less inductance). Through-hole remains better for high-current connectors and mechanically stressed components.

### solder mask

Solder mask is a polymer coating applied over the PCB copper to protect traces from oxidation, prevent solder bridges, and provide electrical insulation. It's typically epoxy-based, applied by screen printing, curtain coating, or spray, then imaged to create openings over pads and vias. Standard color is green, but blue, red, black, white, and matte finishes are available. Solder mask thickness affects impedance and must be considered in controlled-impedance designs. The mask-defined pad technique uses solder mask to define pad size.

### stacked via

Stacked vias are micro-vias drilled directly on top of each other through multiple build-up layers, creating a vertical interconnect tower. Stacking maximizes routing density but requires copper filling of lower vias before stacking subsequent ones, as an unfilled void would cause reliability issues under thermal stress. Stacked via structures are more expensive than staggered vias but necessary for escape routing from ultra-fine-pitch devices. Any-layer HDI typically uses all-stacked construction.

### staggered via

Staggered vias are micro-vias offset horizontally from each other on successive build-up layers, rather than stacked directly above one another. Staggering allows vias to land on copper pads without requiring the lower via to be filled, reducing process complexity and cost. The offset pattern must provide sufficient capture pad area for each via. Staggered vias use more routing space than stacked vias but are adequate for many HDI applications. A mix of stacked and staggered vias is common.

### stripline

Stripline is a transmission line structure where a signal trace on an inner layer is sandwiched between two reference planes (typically ground). The trace is fully embedded in dielectric material, giving better shielding against EMI and crosstalk than microstrip. Stripline is preferred for high-speed differential pairs and sensitive analog signals. The symmetric structure (equidistant from both planes) is called balanced stripline; asymmetric placement is also used. Stripline traces cannot be probed directly, complicating debug.

### surface microstrip

Surface microstrip is a transmission line with a conducting strip on the outer PCB layer, separated from a ground plane by dielectric substrate, with air above the trace. The electromagnetic field exists partially in air (Dk=1) and partially in the dielectric, creating an effective dielectric constant lower than the substrate's rated Dk. This quasi-TEM propagation means the effective Dk for a typical FR-4 board (Dk 4.3) is around 3.3-3.5. Surface microstrip is the most common controlled impedance structure due to easy access for probing, testing, and component placement.

### symmetric stripline

Symmetric stripline (also called centered stripline) positions the signal trace exactly at the geometric center between two parallel reference planes, embedded in homogeneous dielectric. The equal spacing to both planes produces the most predictable impedance and best signal integrity. However, achieving true symmetry is difficult in practice since materials above (typically prepreg) and below (typically core) often have slightly different dielectric properties. Symmetric stripline supports true TEM mode propagation and provides excellent EMI shielding.

### teardrop

Teardrops are filleted transitions that gradually widen a trace where it connects to a pad or via. This tapered shape reduces stress concentration at the junction, improving resistance to thermal cycling and mechanical stress. Teardrops also provide manufacturing margin: if drill registration is slightly off or etching undercuts the trace, the extra copper maintains the connection. Most PCB CAD tools can add teardrops automatically. Specify teardrops for high-reliability designs (IPC Class 3), boards subject to vibration or thermal cycling, and any design where trace-to-pad junctions are near minimum width. The added copper has negligible impact on impedance for most designs.

### thermal relief

Thermal relief is a spoke pattern (typically 4 spokes) connecting a through-hole or via pad to a surrounding copper plane. Without thermal relief, the plane acts as a massive heat sink, making hand soldering nearly impossible and causing cold joints in wave soldering. The spokes provide electrical connection while limiting heat transfer. Spoke width affects current capacity - wider spokes for power connections. Some high-current applications eliminate thermal relief entirely (direct connect) and rely on reflow or controlled soldering processes. Thermal relief design balances electrical performance against manufacturing requirements.

### thermal via

Thermal vias are plated through-holes designed to transfer heat from components to copper planes or the opposite side of the PCB. They're commonly used under QFN and BGA thermal pads to conduct heat to inner ground planes or bottom-side heatsinks. Arrays of 0.3mm thermal vias on 0.6mm pitch can reduce junction temperature by 20-40°C. Vias directly under thermal pads should be plugged or capped to prevent solder wicking during reflow. Vias outside the pad area can be tented with solder mask instead, which costs less. More vias improve thermal conductivity but may weaken the pad structure if too densely packed.

### through-hole

Through-hole technology uses component leads inserted through plated holes and soldered on the opposite side. Choose through-hole over SMD when: mechanical strength matters (connectors see repeated mating cycles, components under mechanical stress), current exceeds SMD package ratings (through-hole handles 3-5A per pin easily), or hand soldering and field repair are expected. Through-hole pads must include thermal relief when connected to planes, otherwise wave soldering will not wet properly. Mixed-technology boards assemble SMT first (reflow), then through-hole (wave or selective soldering).

### trace

A trace is a copper conductor path etched on a PCB layer that connects component pads, vias, or other traces. Trace width determines current-carrying capacity (wider = more current) and affects impedance (wider = lower impedance for same dielectric height). Minimum trace width depends on copper weight and manufacturing capability (typically 75-100 µm for standard, 50 µm for advanced). Trace spacing affects crosstalk and voltage withstand. High-speed traces require controlled impedance and length matching.

### via

A via (vertical interconnect access) is a plated hole that electrically connects traces on different PCB layers. Through-vias span the entire board thickness; blind vias connect an outer layer to inner layers; buried vias connect only inner layers. Via size affects routing density and signal integrity - smaller vias allow tighter routing but cost more. Standard vias are 0.3mm drill/0.6mm pad; micro-vias are ≤0.15mm laser-drilled. Via placement affects impedance (stubs), thermal performance (thermal vias), and HDI capability.

### via filling

Via filling completely fills the via hole with either conductive (copper or silver-filled) or non-conductive (epoxy) material. Conductive fill is required for stacked micro-vias in HDI designs, providing electrical continuity and thermal dissipation. Non-conductive fill is used for via-in-pad where electrical connection through the via isn't needed. Filled vias are typically planarized (ground flat) and may be capped (plated over). Via filling is more thorough than plugging, leaving no void in the hole.

### via plugging

Via plugging fills via holes with non-conductive epoxy paste, providing a barrier against solder wicking and creating a more planar surface. Plugging is required for via-in-pad designs where solder could wick into open vias during reflow, starving the joint. Plugged vias can be capped (plated over) for complete planarization. Via plugging adds cost but is essential for fine-pitch BGA assemblies. The plug material must withstand reflow temperatures without outgassing or failure.

### via stub

A via stub is the unused portion of a through-hole via extending beyond the signal layers it connects. For example, if a via connects layer 1 to layer 4 of an 8-layer board, the portion from layer 4 to layer 8 is a stub. Stubs act as unterminated transmission line branches, causing resonances at frequencies where stub length equals odd multiples of quarter-wavelength. At multi-GHz frequencies, stub effects degrade signal integrity. Solutions include back-drilling (removing stubs), HDI with blind vias, or designing signal layers near the outer layers.

### via tenting

Via tenting covers via holes with solder mask on one or both sides. Tenting protects vias from solder bridging during assembly, prevents contamination, and provides electrical insulation. Use tenting for small vias (≤0.4mm) away from test points when cost is a priority. However, tented vias may not be fully sealed (solder mask may dimple into the hole), so they shouldn't be used where hermetic sealing is needed. For via-in-pad under fine-pitch components, use plugging instead - tenting alone won't prevent solder wicking. Tented vias cannot be probed for testing.

### via-in-pad

Via-in-pad places a via directly within a surface-mount component pad rather than adjacent to it (dog-bone style). This technique is essential for fine-pitch BGAs (≤0.5mm) and QFNs where space between pads is insufficient for fan-out vias. Via-in-pad requires the via to be plugged with non-conductive epoxy, then capped with copper plating to create a flat, solderable surface (VIPPO process). Without plugging, solder wicks into the via during reflow, causing voids and weak joints. Via-in-pad adds 15-25% to fabrication cost but enables higher density and better thermal paths.

### VIPPO

VIPPO (Via-In-Pad Plated Over) places vias directly in component pads, fills them with conductive or non-conductive material, and plates over flat. Essential for fine-pitch BGAs where escape routing requires vias in the pad pattern. Without filling/plating, solder wicks into vias causing insufficient joints. Process: drill via, plate, fill (copper or epoxy), planarize, plate over. Adds cost ($50-200 per panel) but enables dense designs impossible otherwise. Alternative: via-in-pad with capped (non-planar) surface works for some applications at lower cost.

## Technical Properties

Electrical, thermal, and mechanical specifications

### aspect ratio

Aspect ratio is the ratio of hole depth (board thickness) to hole diameter. Higher aspect ratios make it more difficult to achieve uniform copper plating throughout the hole. Standard capability is 8:1 to 10:1 (e.g., 0.2mm hole in 1.6mm board = 8:1). Advanced processes can achieve 12:1 to 15:1. For micro-vias, aspect ratio is typically limited to 0.75:1 to 1:1 due to the laser drilling and plating limitations. Exceeding capability limits can cause barrel cracking and reliability failures.

### barrel crack

A barrel crack is a fracture in the copper plating wall of a plated through-hole, typically caused by Z-axis thermal expansion mismatch between the plating and laminate. During thermal cycling, the laminate expands more than the copper barrel, creating tensile stress that can crack the plating. Barrel cracks cause intermittent opens or increased resistance. Risk factors include high aspect ratio, thin plating, thick boards, and numerous thermal cycles (especially above Tg). High-reliability designs specify minimum plating thickness and controlled CTE materials.

### bow and twist

Bow and twist are measurements of PCB flatness. Bow is the deviation where a board is cylindrically curved (edges curve up while center remains flat, or vice versa). Twist is the deviation where one corner lifts relative to the other three corners. IPC specifies maximum allowable bow and twist (typically 0.75% for surface mount, 1.5% for through-hole). Excessive warpage causes assembly problems: solder paste printing issues, component placement errors, and solder joint opens. Symmetric stackups and proper material handling minimize warpage.

### CAF

Conductive Anodic Filament (CAF) is an electrochemical migration failure where copper ions migrate along the glass fiber/resin interface under voltage bias and humidity, eventually forming a conductive path causing shorts. CAF growth requires voltage, humidity, and a vulnerable path (poor fiber-resin adhesion). Risk factors include high voltage, fine pitch (closer spacing), and poor laminate quality. CAF-resistant laminates use improved glass treatments and resin systems. Testing per IPC-TM-650 evaluates CAF resistance. High-reliability designs specify CAF-resistant materials.

### characteristic impedance

Characteristic impedance (Z₀) is the ratio of voltage to current for a wave traveling along a transmission line. It's determined by trace geometry (width, thickness), dielectric thickness to reference plane, and dielectric constant. For PCB traces, common structures include microstrip (trace on outer layer referenced to plane below) and stripline (trace between two planes). Fabricators typically guarantee controlled impedance within ±10% (e.g., 50Ω ±5Ω). They achieve this by adjusting trace widths during manufacturing to compensate for material and etch variations. Specify your target impedance in your fabrication notes and the fabricator will optimize trace geometry.

### common-mode

Common-mode signals appear identically on both conductors of a differential pair - noise that couples equally to P and N lines. Differential receivers reject common-mode noise (CMRR), which is why differential signaling handles noisy environments well. Common-mode impedance differs from differential impedance and affects EMI. AC coupling capacitor mismatch converts common-mode to differential, degrading signal quality. Common-mode chokes filter common-mode noise on I/O lines. Keep differential pairs tightly coupled and length-matched to minimize common-mode conversion.

### copper weight

Copper weight describes copper foil thickness using the weight of copper in one square foot. Standard weights are 0.5 oz (18 µm), 1 oz (35 µm), and 2 oz (70 µm). Heavier copper carries more current and dissipates heat better but limits fine-feature resolution. Plating adds ~25 µm to the finished copper thickness. High-current applications may use 3-10 oz copper, requiring special processing. Trace width tables for current capacity are based on copper weight and temperature rise.

### crosstalk

Crosstalk is electromagnetic coupling between adjacent traces, where a signal on one trace (aggressor) induces noise on a neighboring trace (victim). Forward crosstalk travels in the same direction as the signal; backward crosstalk travels in the opposite direction. Crosstalk increases with trace length, coupling distance, and signal speed. Mitigation includes wider spacing (3x line width rule of thumb), ground shields between traces, stripline routing (better shielding than microstrip), and shorter parallel runs. Crosstalk causes timing jitter and reduces noise margin.

### current capacity

Current capacity (ampacity) is the maximum current a trace can carry within acceptable temperature rise - typically 10°C, 20°C, or 30°C above ambient. Depends on: trace width, copper thickness, layer location (external vs internal), and acceptable heating. IPC-2152 provides charts and formulas. Rule of thumb for 1oz external: 1A per 0.25mm width at 10°C rise. Internal traces carry ~50% less due to poor heat dissipation. For high current, use multiple vias in parallel, thicker copper (2-4oz), or copper pours. Thermal simulation validates high-power designs.

### differential impedance

Differential impedance (Zdiff) is the impedance measured between the two conductors of a differential pair when driven with opposite-polarity signals. It equals approximately 2x the odd-mode impedance of each trace (exactly 2x for symmetric coupling). Common differential impedance targets are 90 ohms (USB 2.0/3.0, HDMI), 85 ohms (PCIe, SATA), and 100 ohms (Ethernet, LVDS). Differential impedance depends on trace geometry, spacing between traces, dielectric thickness, and material properties. Tighter coupling (smaller gap) reduces differential impedance.

### EMC

Electromagnetic Compatibility (EMC) is the ability of electronic equipment to operate without causing electromagnetic interference to other equipment and without being susceptible to EMI from external sources. EMC includes both emissions (outgoing interference) and immunity/susceptibility (resistance to incoming interference). Product certification requires passing EMC tests for radiated and conducted emissions and immunity. PCB design significantly affects EMC performance through proper grounding, filtering, shielding, and layout practices.

### EMI

Electromagnetic Interference (EMI) is unwanted electromagnetic energy that disrupts electronic equipment operation. EMI can be conducted (through power lines or cables) or radiated (through space). PCB design affects EMI through ground plane integrity, high-speed signal routing, and enclosure grounding. Common EMI mitigation includes proper stackup design, controlled impedances, filtering on I/O lines, and keeping high-speed signals on internal stripline layers. Regulatory compliance (FCC, CE) requires meeting EMI emission limits.

### even-mode impedance

Even-mode impedance (Zeven) is the impedance seen by each individual trace in a coupled pair when both traces are driven with identical signals (common mode). The coupling between traces raises the effective impedance compared to an isolated trace because the like-polarity fields partially cancel. Even-mode impedance increases as trace spacing decreases. Common-mode impedance of the pair equals Zeven/2. While differential signals ideally see only odd-mode impedance, any common-mode noise or signal imbalance sees even-mode impedance, which affects common-mode rejection and EMI performance.

### fiber weave effect

Fiber weave effect refers to the signal integrity impact of periodic dielectric constant variation in glass-reinforced laminates. Glass fiber bundles have different Dk (~6) than the surrounding resin (~3), creating a pattern of Dk variation. Traces routed over glass bundles see different impedance than traces over resin-rich regions. This causes timing skew between differential pair legs and impedance ripple. Mitigation includes rotating the board relative to the trace direction, using spread glass materials, or non-woven reinforcement for critical applications.

### high-Dk

High-Dk (high dielectric constant) materials have Dk values significantly above standard FR-4's 4.2-4.5. Applications: embedded capacitance (Dk 10-35 for FaradFlex, Interra), antenna miniaturization (higher Dk shrinks antenna dimensions), and filter design. Trade-offs: higher Dk usually means higher loss (Df), and signal propagation slows (velocity ≈ c/√Dk). Cost increases substantially with Dk. Materials include ceramic-filled PTFE, barium titanate composites, and specialty laminates. Use high-Dk strategically for specific layers or applications, not throughout the stackup.

### impedance

Impedance is the total opposition to alternating current, combining resistance, inductance, and capacitance. In PCB design, controlled impedance transmission lines are essential for high-speed signals to prevent reflections and signal degradation. Common values are 50Ω single-ended and 90-100Ω differential. Impedance depends on trace width, dielectric thickness, dielectric constant, and copper thickness. Fabricators typically guarantee ±10% impedance tolerance, achieved through controlled material selection and trace width compensation.

### insertion loss

Insertion loss measures the reduction in signal power as it travels through a PCB transmission line, expressed in dB per unit length (typically dB/inch). It results from conductor loss (resistance of copper traces) and dielectric loss (energy absorbed by laminate material). Insertion loss increases with frequency, trace length, and narrow trace width. For high-speed signals (>10 Gbps), low-loss materials with lower Df are essential to maintain signal quality over longer trace lengths. Eye diagram closure is a visible effect of excessive insertion loss.

### loss tangent

Loss tangent (tan δ) is identical to dissipation factor (Df), measuring the ratio of energy dissipated to energy stored in a dielectric per AC cycle. It's expressed as the tangent of the phase angle between voltage and current in a capacitor made from the material. Lower loss tangent means less signal attenuation at high frequencies. Standard FR-4 has tan δ around 0.02; low-loss materials like Rogers RO4003C achieve 0.0027; PTFE materials can be below 0.001. Loss tangent typically increases with frequency and temperature.

### odd-mode impedance

Odd-mode impedance (Zodd) is the impedance seen by each individual trace in a coupled pair when driven with equal but opposite signals (differential mode). The coupling between traces lowers the effective impedance compared to an isolated single-ended trace. Differential impedance equals approximately 2x Zodd (exactly 2x for symmetric coupling). For a 100-ohm differential pair, each trace sees about 50 ohms odd-mode impedance. Odd-mode impedance decreases as trace spacing decreases (tighter coupling), which is why differential pairs are routed with controlled, tight spacing.

### quasi-TEM

Quasi-TEM (quasi-transverse electromagnetic) describes signal propagation in microstrip and similar structures where the electromagnetic field exists in two different media (air and dielectric). Unlike true TEM mode in stripline where fields are purely transverse, microstrip fields have small longitudinal components because the wave travels at different speeds in air versus dielectric. This causes the effective dielectric constant and phase velocity to vary somewhat with frequency, creating dispersion at high frequencies. For most PCB applications below 10 GHz, the quasi-TEM approximation is accurate enough for impedance calculations.

### reflection

Reflection occurs when a signal encounters an impedance change (discontinuity) in a transmission line. Part of the signal energy bounces back toward the source rather than continuing to the load. Reflection coefficient ρ = (Z_load - Z₀)/(Z_load + Z₀) determines reflection magnitude: matched impedance (ρ=0) has no reflection; open circuit (ρ=1) reflects fully in phase; short circuit (ρ=-1) reflects fully inverted. Reflections cause ringing, overshoot, and signal integrity problems. Minimizing reflections requires impedance matching and avoiding discontinuities.

### reliability

PCB reliability encompasses the board's ability to function correctly over its intended lifetime under expected conditions. Key factors: material selection (Tg, Td, CAF resistance), design choices (annular ring, via reliability, thermal management), and manufacturing quality (plating thickness, cleanliness). IPC Class 3 specifies requirements for high-reliability applications. Testing includes thermal cycling, microsection analysis, and accelerated life testing. Reliability failures include barrel cracks, pad lift, CAF shorts, and solder joint fatigue. Designing for reliability costs more upfront but prevents field failures.

### resin-rich region

Resin-rich regions form between tightly-spaced differential traces during PCB lamination. As prepreg flows under heat and pressure, pure resin (with different dielectric properties than glass-reinforced prepreg) fills the narrow gaps between conductors. This creates a zone with lower Dk than the surrounding material, affecting differential impedance calculations. The effect becomes significant for fine-pitch differential pairs where the gap is narrow enough to exclude glass fibers. Field solvers like Polar Si9000e model this with a separate Rer (resin-rich dielectric constant) parameter, typically 0.3-0.5 lower than the bulk prepreg Dk.

### sheet resistivity

Sheet resistivity measures the resistance of a thin conductive film, expressed in ohms per square (Ω/□). To calculate an embedded resistor: R = sheet resistivity × (length ÷ width). Example: with 100 Ω/□ material, a resistor 2mm long and 0.5mm wide gives 100 × (2 ÷ 0.5) = 400Ω. A square resistor (length = width) always equals the sheet resistivity regardless of size. Available Ohmega-Ply materials range from 25 to 250 Ω/□. Choose higher sheet resistivity for large values in small areas, but note this reduces current handling capacity.

### signal integrity

Signal integrity refers to maintaining electrical signal quality from driver to receiver, ensuring reliable data transmission. SI concerns include impedance matching (preventing reflections), crosstalk (interference between traces), insertion loss (signal attenuation), and timing (skew in parallel buses or differential pairs). Signal integrity becomes critical as data rates increase and rise times decrease. SI analysis uses simulation tools to model transmission lines, verify timing margins, and predict eye diagram quality.

### solderability

Solderability measures how well solder wets and bonds to a surface. Good solderability requires: clean surface (no oxides, contamination), appropriate surface finish, and correct flux/temperature. Surface finishes degrade over time - OSP lasts 6 months, ENIG 12+ months. Testing per IPC J-STD-003 verifies solderability before assembly. Poor solderability causes dewetting, non-wetting, and unreliable joints. Factors affecting solderability: surface finish type, storage conditions, contamination, and intermetallic formation. Baking boards before assembly removes absorbed moisture that causes solderability problems.

### TCR

Temperature Coefficient of Resistance (TCR) describes how much a resistor's value changes with temperature, expressed in parts per million per degree Celsius (ppm/°C). Positive TCR means resistance increases with temperature. For embedded resistors, TCR matters for precision applications where temperature variations affect circuit performance. Thin-film embedded resistors (NiCr) typically achieve TCR of ±100 ppm/°C or better, while thick-film carbon may have TCR of ±250-500 ppm/°C. Lower TCR indicates better temperature stability.

### Td

Decomposition Temperature (Td) is the temperature at which a PCB laminate begins to chemically decompose, measured as the temperature at which 5% weight loss occurs (by TGA test). Td is always higher than Tg and represents a hard limit; exceeding Td causes permanent damage. Standard FR-4 has Td around 310-330°C, while high-performance materials may exceed 350°C. Td matters for lead-free assembly where peak reflow temperatures approach 260°C, leaving less margin than leaded assembly. Multiple reflow cycles cumulate thermal stress.

### TDR

Time Domain Reflectometry (TDR) measures transmission line impedance by sending a fast-rise pulse down the line and analyzing reflections. Impedance discontinuities cause partial reflections - the magnitude and polarity indicate whether impedance increased or decreased, and the timing reveals the location. PCB fabricators use TDR to verify controlled impedance on test coupons, typically guaranteeing ±10% (standard) or ±5% (tight tolerance). Industry-standard equipment includes sampling oscilloscopes like the Tektronix DSA8300 series with TDR modules, achieving rise times under 20 ps for sub-millimetre spatial resolution. TDR results appear in impedance test reports delivered with controlled-impedance boards.

### TEM mode

Transverse electromagnetic (TEM) mode is the ideal propagation mode for transmission lines where both electric and magnetic fields are entirely perpendicular to the direction of signal propagation - no field components exist in the direction of travel. Stripline supports true TEM mode because the signal is completely surrounded by homogeneous dielectric. TEM propagation has no cutoff frequency and no dispersion (phase velocity is constant with frequency). Microstrip only approximates TEM (quasi-TEM) because part of the field travels through air with a different dielectric constant than the substrate.

### Tg

Glass Transition Temperature (Tg) is the temperature at which an amorphous polymer transitions from a hard, glassy state to a soft, rubbery state. For PCB laminates, standard FR-4 has Tg of 130-140°C, mid-Tg is 150-160°C, and high-Tg is 170-180°C. Above Tg, the Z-axis CTE increases dramatically (from ~50 ppm/°C to ~250 ppm/°C), stressing plated through-holes. Lead-free assembly typically requires Tg ≥150°C to withstand higher reflow temperatures.

### thermal conductivity

Thermal conductivity measures heat transfer through a material (W/m·K). Standard FR-4: 0.3 W/m·K (poor). Aluminum: 205 W/m·K. Copper: 385 W/m·K. For PCBs, heat conducts through copper (traces, planes, vias) much better than through dielectric. Thermal vias transfer heat between layers. Metal-core PCBs use aluminum or copper for heat spreading. High-power designs need thermal analysis - component junction temperature depends on thermal path to ambient. Some specialty materials (ceramic-filled, aluminum nitride) offer improved thermal conductivity at premium cost.

### thermal cycling

Thermal cycling describes repeated temperature fluctuations experienced by a PCB during operation or environmental exposure. Each heating and cooling cycle causes materials to expand and contract at different rates according to their CTE. Over time, this mechanical stress leads to solder joint fatigue, via barrel cracking, or delamination at interfaces between dissimilar materials. Design mitigations include: selecting materials with matched CTE, using filled vias for high-aspect-ratio holes, adding teardrops at pad-trace junctions to reduce stress concentration, and specifying high-Tg laminates. Thermal cycling tests (e.g., -40°C to +125°C for 1000 cycles) simulate years of field use during qualification.

### transmission line

A transmission line is a signal path where the propagation delay matters - typically when trace length exceeds 1/10 of the signal's rise time equivalent wavelength. At this point, the trace acts as a distributed impedance rather than a simple wire. Proper termination prevents reflections. PCB transmission lines include microstrip (trace over plane), stripline (trace between planes), and coplanar waveguide (trace with adjacent ground). Characteristic impedance depends on trace geometry and dielectric properties. Most digital signals above 100MHz and all RF signals require transmission line design.

### virtual ground

Virtual ground is the effective ground reference that exists equidistant between two differentially-driven traces, even without a physical ground plane. When traces carry equal but opposite signals, every point equidistant from both conductors sits at 0V potential, creating an effective ground reference without physical copper. This allows differential pairs to function under Ethernet connectors where no adjacent plane exists, on two-layer boards, or in cost-sensitive designs without continuous ground planes. Impedance can be calculated as a surface microstrip with H equal to half the trace separation, then doubling the result.

### Z-axis CTE

Z-axis CTE (coefficient of thermal expansion) is the expansion rate through the PCB thickness. Unlike X-Y axes (constrained by fiberglass), Z-axis expansion is resin-dominated and much higher. Below Tg, typical FR-4 has Z-axis CTE of 50-70 ppm/°C; above Tg it can exceed 250 ppm/°C. High Z-axis CTE stresses plated through-holes during thermal cycling, potentially causing barrel cracks. Thicker boards, higher aspect ratio vias, and more thermal cycles increase failure risk. Low-CTE materials are used for high-reliability applications.

## Specialized Technologies

HDI, embedded components, RF, flex circuits

### any-layer

Any-layer (or every-layer interconnect) HDI uses micro-vias throughout the stackup, allowing vias between any two adjacent layers. Unlike conventional HDI with specific build-up sequences (1+N+1, 2+N+2), any-layer construction typically uses all cores or RCC build-up with no mechanical through-holes. This maximizes routing freedom and density, enabling escape routing from ultra-fine-pitch components. Stacked micro-vias must be copper-filled for reliability. Any-layer is the most advanced HDI type, used in smartphones and other high-density applications.

### embedded capacitor

Embedded capacitors are capacitive elements built into the PCB using thin, high-dielectric-constant materials between power and ground planes. Technologies include laminated high-Dk sheets (like 3M C-Ply or Oak-Mitsui FaradFlex) and discrete capacitor embedding. Embedded capacitance provides power supply decoupling with lower inductance than surface-mount caps, effective above 100 MHz where discrete caps lose effectiveness. Capacitance values are typically 0.5-2 nF/sq inch, suitable for bulk decoupling, not precision timing.

### embedded component

Embedded components are built into the PCB substrate rather than mounted on the surface. Embedded passives use resistive foil (Ohmega-Ply) or high-Dk dielectric for capacitors. Embedded actives place bare die in cavities with micro-via connections. Benefits: reduced size, shorter interconnects (better signal integrity), improved reliability (no solder joints). Drawbacks: no rework possible, limited supplier base, higher NRE. Used in military/aerospace, medical implants, and ultra-compact consumer electronics. Requires specialized design tools and manufacturing processes.

### embedded resistor

Embedded resistors are resistive elements built into the PCB substrate rather than surface-mounted. They're created using resistive foil (like Ohmega-Ply with NiCr alloy) laminated into the stackup, then imaged and etched to define resistor geometry, or using carbon paste screen-printed onto inner layers. Benefits include size reduction, improved signal integrity (no parasitic inductance), and reliability. Tolerances are typically ±10-25% (carbon) or ±5-10% (thin-film foil). Values range from 10Ω to 10MΩ depending on technology.

### flex PCB

Flexible PCBs (FPCs or flex circuits) use thin, flexible polyimide substrate (typically 12.5-50 µm) with copper traces and polyimide coverlay instead of rigid laminate and solder mask. Flex circuits can be single-sided, double-sided, or multilayer. They're classified as static flex (bent once during assembly) or dynamic flex (repeatedly bent in operation). Dynamic flex requires careful trace routing (perpendicular to bend), radiused corners, and no plated through-holes in the bend zone. Flex enables compact packaging and moving connections.

### metal-core

Metal-core PCBs (MCPCB) use an aluminum or copper base layer for thermal management. Heat from components conducts through a thin dielectric (0.075-0.2mm) into the metal core, which spreads and dissipates it. Thermal conductivity: aluminum ~1-2 W/mK for the dielectric layer, copper core ~380 W/mK. Used for high-power LEDs, motor drives, and power supplies. Single-sided is most common; double-sided requires insulated vias. Aluminum is standard; copper costs more but conducts better. The dielectric layer is the thermal bottleneck - thinner is better but reduces voltage isolation.

### planar transformer

A planar transformer implements windings as spiral traces on PCB layers rather than wound wire, with a magnetic core assembled around the PCB. Planar construction enables very low profile (often <10mm height), high power density, excellent repeatability, and integrated assembly. Multiple PCB layers connect in series or parallel for primary and secondary windings. Planar magnetics are common in DC/DC converters, with proper design achieving efficiencies over 95%. Interleaved winding structures minimize leakage inductance.

### RFID

Radio-Frequency Identification (RFID) uses electromagnetic fields to automatically identify and track tags attached to objects. RFID systems consist of tags (with antenna and chip) and readers. Tags can be passive (powered by reader's RF field), active (battery-powered), or semi-passive. PCB technology is used for RFID antennas on both rigid and flexible substrates. Operating frequencies include LF (125-134 kHz), HF (13.56 MHz), UHF (860-960 MHz), and microwave (2.45 GHz). Antenna design requires precise impedance matching and careful material selection for the target frequency.

### rigid-flex

Rigid-flex PCBs combine rigid FR-4 sections with flexible polyimide circuits in a single integrated structure. The flex regions allow bending for packaging in tight enclosures, replace connectors and cables, and improve reliability by eliminating solder joints. Rigid-flex requires careful design of the transition zones between rigid and flex areas, with stiffeners and controlled bend radii. Construction can be bookbinder style (flex layers continuous through rigid) or loose-leaf style (flex attached at edges). Higher cost but enables form factors impossible with rigid boards and cable assemblies.

## Standards & Certifications

Industry standards and compliance requirements

### AEC-Q100

AEC-Q100 is the Automotive Electronics Council's standard for stress test qualification of integrated circuits in automotive applications. It establishes temperature grading (Grade 0 being most stringent: -50°C to +150°C, Grade 3 for 0°C to +85°C) and reliability test requirements ensuring semiconductors withstand extreme automotive environments. When specifying ICs for automotive PCBs, require AEC-Q100 qualified parts and specify the grade matching your operating environment. Under-hood applications typically need Grade 1 (-40°C to +125°C) or Grade 0.

### AEC-Q200

AEC-Q200 is the global standard for stress resistance that passive electronic components (resistors, capacitors, inductors) must meet for automotive use. Components undergo rigorous temperature cycling, humidity exposure, vibration, mechanical shock, and electrical stress testing. When designing automotive electronics, specify AEC-Q200 qualified passives. Regular commercial-grade components may fail in automotive environments due to temperature extremes, vibration, and long operational life requirements (15+ years).

### AS6081

AS6081 establishes requirements and practices to mitigate the risk of counterfeit parts entering the aerospace supply chain. Created in response to increasing fraudulent electronic parts in aerospace applications, it builds upon AS9100/AS9120 certifications with additional anti-counterfeiting controls including supply chain traceability, inspection requirements, and testing protocols. Critical for any aerospace electronics procurement. If your aerospace customer requires AS6081 compliance, your supply chain must demonstrate counterfeit prevention measures.

### AS9100

AS9100 is the premier aerospace quality management standard developed by the International Aerospace Quality Group. It includes all ISO 9001:2015 requirements plus aerospace-specific requirements for operational risk management, design and development activities, supply chain management, and complete traceability. Endorsed by FAA, DoD, NASA, and major aerospace OEMs. If you're supplying PCBs for aerospace applications, your fabricator needs AS9100 certification. Current version is AS9100 Rev D.

### compliance

Compliance encompasses regulatory requirements (RoHS, REACH, UL) and industry standards (IPC, ISO) that PCBs and assemblies must meet. RoHS restricts hazardous substances; UL certifies flammability; IPC defines quality classes. Compliance affects material selection (lead-free, halogen-free), testing (flammability, electrical), and documentation (certificates of conformance, material declarations). Non-compliance can block market access or create liability. Design for compliance early - retrofitting lead-free or meeting unexpected requirements is expensive. Specify compliance requirements in fabrication drawings.

### Conflict Minerals

Conflict minerals regulations (Dodd-Frank Act Section 1502 and EU 2017/821) require companies to disclose use of 3TG minerals (tin, tantalum, tungsten, gold) from conflict-affected regions. Tin is used in solder and surface finishes, tantalum in capacitors, tungsten in some components, and gold in ENIG finishes and wire bonding. Your customers may require Conflict Minerals Reporting Templates (CMRTs) from your supply chain. Large OEMs typically have conflict minerals compliance programs you'll need to participate in.

### ESD S20.20

ANSI/ESD S20.20 provides administrative and technical requirements for establishing an ESD control program protecting electrical and electronic parts susceptible to damage from electrostatic discharge. It covers Human Body Model discharges at 100V or higher, Charged Device Model discharges at 200V or higher, and isolated conductor voltages at 35V or higher. Over 1,900 facilities are certified worldwide. For PCB assembly, ESD S20.20 certification ensures proper grounding, humidity control, and handling procedures. It integrates with ISO 9001 and AS9100 quality systems.

### IATF 16949

IATF 16949 is the global automotive industry quality management standard developed by the International Automotive Task Force. Based on ISO 9001 with additional automotive-specific requirements for continual improvement, defect prevention, and supply chain waste reduction. Mandatory for most automotive Tier 1 and Tier 2 suppliers, including PCB manufacturers serving the automotive sector. The standard's PPAP (Production Part Approval Process) requirements mean extensive documentation before production begins. If you're designing automotive electronics, your PCB supplier needs IATF 16949 certification.

### IPC

IPC (originally Institute for Printed Circuits, now IPC International) is the global trade association that develops standards for the electronics manufacturing industry. Key standards include IPC-A-600 (acceptability of PCBs), IPC-6012 (qualification and performance of rigid PCBs), IPC-6013 (flex/rigid-flex), and IPC-A-610 (acceptability of electronic assemblies). IPC Class 2 covers general electronics, Class 3 covers high-reliability products like medical and aerospace.

### IPC Class

IPC Classes define PCB quality and reliability requirements. Class 1: general electronics, limited life (disposables, toys). Class 2: dedicated service electronics, extended life (computers, telecom) - most commercial products. Class 3: high reliability, continued performance critical (medical, aerospace, military). Higher classes require tighter tolerances: better annular rings, plating uniformity, cleanliness, and documentation. Class 3 boards cost 20-50% more than Class 2 due to inspection, testing, and yield loss. Specify Class in fabrication notes. Class 2 is default; specify Class 3 only when reliability requirements demand it.

### IPC Class 2

IPC Class 2 defines acceptance criteria for dedicated service electronic products where continued performance and extended life are required, but not critical. This covers most commercial and industrial electronics: computers, telecommunications, instrumentation, and business machines. Class 2 allows some imperfections that would be rejected in Class 3, with minimum annular ring of 50 µm (vs. 75 µm for Class 3). Most commercial PCBs are manufactured to Class 2 requirements unless higher reliability is specified.

### IPC Class 3

IPC Class 3 defines acceptance criteria for high-performance electronic products where continued performance or performance-on-demand is critical, and downtime cannot be tolerated. Applications include life-support medical equipment, flight-critical avionics, and military systems. Class 3 requires tighter tolerances, better plating quality, larger annular rings, and more thorough inspection. Manufacturing costs are higher due to lower yields and additional testing. Class 3 is specified when reliability is paramount.

### IPC-2221

IPC-2221 is the foundational design standard for all PCB types, establishing generic requirements for component mounting and interconnection structures. It covers conductor spacing and clearance (including high-voltage requirements up to 500V), trace width for current capacity (the famous charts), material selection, thermal management, via structures, and test coupon requirements. When your CAD tool flags a spacing violation, it's likely checking against IPC-2221 rules. The standard is the master reference that all sectional design standards (IPC-2222 for rigid, IPC-2223 for flex, IPC-2226 for HDI) build upon.

### IPC-2223

IPC-2223 establishes specific design requirements for flexible and rigid-flex printed boards when used with IPC-2221. It addresses bend radius requirements (minimum 6x thickness for dynamic flex, 3x for static), pad and via placement relative to flex zones (keep them out of bend areas), coverlay specifications, stiffener design, and structural requirements unique to flexible circuits. If you're designing flex, this standard prevents the common mistakes that cause flex failures. Current version is IPC-2223E.

### IPC-2226

IPC-2226 establishes design requirements for high-density interconnect boards featuring microvias, fine lines, and compact layouts. It provides guidelines for microvia formation (laser drilling parameters), metallization requirements, signal/power/ground layer distribution, and dielectric separation. Required reading when designs use fine-pitch BGAs (below 0.5mm pitch) or microvia technology. The standard helps you design HDI structures that can actually be manufactured reliably.

### IPC-2581

IPC-2581 (also known as DPMX - Digital Product Model Exchange) provides a unified XML-based data format for exchanging complete PCB design and manufacturing information. It consolidates artwork, drill data, stackup, netlist, BOM, pick-and-place, and assembly instructions into a single intelligent file - replacing the traditional multi-file Gerber approach. Benefits include reduced data errors, bidirectional DFM communication, and support for Industry 4.0 automation. While Gerber remains dominant, IPC-2581 adoption is growing. Ask your fabricator if they accept IPC-2581 files.

### IPC-4101

IPC-4101 is the comprehensive specification for PCB base materials (laminates and prepregs). It contains over 70 detailed specification sheets ('slash sheets') defining thermal, mechanical, and electrical properties of different material grades including FR-4, high-Tg, low-Dk/Df, and lead-free compatible materials. Specifying a slash sheet number (e.g., 'IPC-4101/126' for standard FR-4, '/129' for high-Tg) is the proper way to designate laminate requirements in your fab notes. This removes ambiguity about which material your fabricator should use.

### IPC-6012

IPC-6012 establishes qualification and performance requirements for rigid printed board fabrication. It covers single-sided, double-sided, and multilayer boards with or without plated-through holes, blind/buried vias, and metal core constructions. The specification defines structural integrity, conductor requirements, hole quality, electrical properties, surface finishes, and testing frequency. When specifying PCBs, reference 'IPC-6012 Class 2' or 'Class 3' to invoke the appropriate acceptance criteria. Class 2 suits most commercial products; Class 3 is for medical, aerospace, and military where reliability is critical. Current version is IPC-6012F (2023).

### IPC-6013

IPC-6013 is the qualification and performance specification for flexible and rigid-flex printed boards. It classifies flex circuits by type (based on layer complexity) and usage class (based on flex requirements). The specification addresses coverlay integrity, stiffeners, bend radius, flex endurance, and acceptable flex-specific defects like cracks in bend areas. If you're designing flex or rigid-flex, your fabricator should be certified to IPC-6013. Specify the flex type (1-4) and class to ensure the board survives its intended flexing cycles. Current version is IPC-6013E (2021).

### IPC-6018

IPC-6018 covers qualification and performance of high-frequency printed boards for RF, microwave, and millimeter-wave applications. It addresses specialized substrate requirements (PTFE, ceramic-filled materials), dielectric constant tolerances (typically ±2-5%), insertion loss limits, and dimensional stability under temperature. For designs operating above 1 GHz where signal integrity is critical, IPC-6018 provides the framework for qualifying your fabricator's RF capability. Current version is IPC-6018D (2022).

### IPC-7711/7721

IPC-7711/7721 is the comprehensive procedural guide for reworking and repairing printed board assemblies. IPC-7711 covers rework procedures (component removal and replacement, solder bridge removal). IPC-7721 covers repair procedures (conductor repair, pad repair, plated hole repair, laminate repair). The standard defines skill levels required for each procedure and provides acceptance criteria. If your product needs field repair capability or you're setting up a rework station, this standard defines the proper techniques. Current version is IPC-7711/7721D (2024).

### IPC-A-600

IPC-A-600 is the definitive illustrated guide for visual acceptance criteria of bare printed circuit boards. The four-color document provides photographs showing target, acceptable, and nonconforming conditions for surface quality, hole integrity, conductor dimensions, solder mask, laminate condition, and plating quality. When you specify 'IPC-A-600 Class 2' or 'Class 3' in procurement docs, you're telling the fabricator exactly what defects are acceptable. Class 2 allows minor imperfections (non-functional); Class 3 requires near-perfect boards for high-reliability applications. Every incoming inspection team should have the current version on their bench.

### IPC-A-610

IPC-A-610 is the global standard for evaluating assembled PCBs. It provides visual acceptance criteria for solder joint quality, component placement, mechanical assembly, wire connections, and cleanliness across three product classes. When your assembler says they work to 'IPC-A-610 Class 2', they're committing to specific solder fillet heights, component alignment tolerances, and cleanliness levels. Class 3 adds requirements for high-reliability products. The standard covers everything from through-hole and SMT soldering to BGA inspection and conformal coating. Current version is IPC-A-610J (2024).

### IPC-D-356

IPC-D-356 is a data format standard for transmitting bare board electrical test information between design systems and electrical test equipment. It provides data structures for netlist information suitable for computer-aided test processing. When your fabricator performs electrical testing (flying probe or bed-of-nails), they typically use IPC-D-356 format to define test points. Current version is IPC-D-356B. Most CAD tools can export this format automatically.

### ISO 13485

ISO 13485 is the quality management standard specifically for medical device manufacturers. It has strict requirements for risk management, rigorous inspection and traceability for implantable devices, and validation processes beyond ISO 9001. Mandatory for PCB manufacturers supplying medical device components - pacemakers, diagnostic equipment, patient monitors, surgical robots. If you're designing medical electronics, your PCB supplier must hold ISO 13485 certification. Current version is ISO 13485:2016.

### ISO 14001

ISO 14001 is the international standard for environmental management systems. For PCB manufacturers, it requires systematic management of chemicals, wastewater, and energy consumption - proper handling and disposal of hazardous chemicals (etchants, photoresists, plating solutions) and wastewater treatment. Often paired with RoHS/REACH compliance requirements. If your customers require environmental responsibility documentation, ISO 14001 certification demonstrates your supply chain meets recognized environmental standards. Current version is ISO 14001:2015.

### ISO 9001

ISO 9001 is the baseline quality management certification for PCB manufacturers. It establishes criteria for a quality management system ensuring consistent delivery of products meeting customer and regulatory requirements. The standard requires documented procedures, systematic quality checks, defect prevention, and continuous improvement. Virtually all professional PCB procurement requires ISO 9001 certification as the minimum. It doesn't guarantee technical capability, but it ensures the fabricator has controlled processes and traceability. Current version is ISO 9001:2015.

### J-STD-001

J-STD-001 is the globally recognized standard specifying materials, methods, and acceptance criteria for producing quality soldered interconnections. It defines process controls that complement IPC-A-610's inspection criteria. The standard covers flux and solder materials, soldering methods (hand, wave, reflow), solder joint requirements, and process documentation across three product classes. When your assembler claims J-STD-001 certification, they're committing to documented soldering procedures and trained operators. Current version is J-STD-001J (2024). Often referenced alongside IPC-A-610 in assembly specifications.

### MIL-PRF-31032

MIL-PRF-31032 is the current DoD performance specification establishing general requirements for all types of military PCBs (rigid, flex, rigid-flex). It introduces the Qualified Manufacturers List (QML) program allowing manufacturers to implement best commercial practices while meeting military performance needs. QML certification requires establishing a Technical Review Board and ongoing DLA certification. If you're designing for military applications, your fabricator must be on the QML for MIL-PRF-31032.

### MIL-PRF-55110

MIL-PRF-55110 is the legacy specification (predecessor to MIL-PRF-31032) for rigid single-sided, double-sided, and multilayer printed wiring boards for military applications. Still required for legacy military programs where original specifications call out 55110. New designs should use MIL-PRF-31032. If you're supporting existing military equipment, check whether the original drawings specify 55110 or 31032.

### REACH

REACH is the EU's comprehensive chemical regulation requiring registration of all chemical substances manufactured or imported into the EU. It maintains a Substances of Very High Concern (SVHC) list of 200+ substances that require disclosure if present above 0.1% by weight. REACH has broader scope than RoHS, affecting nearly every industry using chemicals. For PCB procurement, REACH compliance requires material declarations from your supply chain. Your customers may require REACH compliance statements, especially for products sold in the EU.

### RoHS

Restriction of Hazardous Substances (RoHS) is an EU directive (2002/95/EC, updated as 2011/65/EU) that restricts the use of lead, mercury, cadmium, hexavalent chromium, PBB, and PBDE in electrical equipment. RoHS compliance requires lead-free solder (typically SAC alloys) with higher reflow temperatures (~260°C peak vs ~230°C for leaded), necessitating high-Tg laminates and surface finishes that withstand multiple lead-free reflow cycles.

### UL

Underwriters Laboratories (UL) is a safety certification organization that tests products for safety hazards. For PCBs, UL certification verifies the laminate meets flammability requirements (UL 94 V-0 means the material self-extinguishes within 10 seconds and doesn't drip flaming particles). UL maintains a database of certified materials and fabricators. UL recognition (UL marking on boards) is required for many end products sold in North America. The UL file number (E-number) identifies the certified construction.

### UL 796

UL 796 is the primary UL safety standard for rigid and flexible printed wiring boards. It covers materials, construction, and performance testing including flammability, thermal endurance, electrical insulation, and mechanical strength. The standard evaluates PCBs for safe operation under normal and abnormal conditions. UL recognition (the UL marking on boards) is required for many end products sold in North America. Your fabricator's UL file number (E-number) identifies their certified constructions.

### UL 94

UL 94 classifies plastics based on flammability characteristics. Critical for PCB base materials, with ratings including V-0 (self-extinguishes within 10 seconds, no flaming drips - standard for FR-4), V-1 (self-extinguishes within 30 seconds), V-2 (allows non-flaming drips), and HB (slow-burning horizontal test). When you specify FR-4, you're getting UL 94 V-0 rated material. For consumer products, UL 94 V-0 is typically required. Check with your certification requirements - some applications accept V-1 or V-2 ratings.

### WEEE

WEEE (Waste Electrical and Electronic Equipment) is an EU directive regulating collection, recycling, and recovery of end-of-life electrical and electronic equipment. It requires producers to register with national authorities, finance collection and disposal, and meet recycling targets. Products must bear the 'crossed out wheeled bin' symbol indicating they shouldn't go in regular waste. For electronics manufacturers, WEEE compliance affects product labeling and requires participation in take-back schemes for products sold in the EU.

## Design Considerations

Design rules, trade-offs, and performance metrics

### AC coupling

AC coupling uses series capacitors to pass AC signal components while blocking DC voltage between circuits. It's essential when driver and receiver have different DC bias levels. For PCB layout, place coupling capacitors close to receivers to minimize stub length. On differential pairs, use matched capacitor values (±5% or better) to avoid introducing skew between P and N lines. High-speed serial links (PCIe, USB, Ethernet) typically require 100nF AC coupling caps in 0402 or smaller packages. Check your protocol specification for capacitor requirements and placement guidelines.

### bend radius

Bend radius is the minimum radius a flex circuit can bend without damage. Rule of thumb: minimum bend radius equals 10x material thickness for dynamic flexing (repeated bending), 6x for static flex (bend once and stay). Tighter bends stress copper, causing cracks and failures. Single-layer flex bends tighter than multilayer. Placing copper at the neutral bend axis reduces stress. Stiffeners prevent bending in component areas. I-beam (hatched) copper patterns improve flex life. For rigid-flex, transition zones between rigid and flex sections need careful design to avoid stress concentration.

### clearance

Clearance is the minimum allowed spacing between conductive elements (traces, pads, vias, planes). Clearance rules derive from two considerations: electrical (voltage withstand, creepage distance) and manufacturing (etch capability, yield). High-voltage designs require larger clearances per IPC-2221 tables based on voltage and coating. Standard PCB fabrication maintains 100 µm (4 mil) minimum spacing for 1 oz copper; finer spacing requires advanced processes. Clearance also affects crosstalk between adjacent traces.

### controlled impedance

Controlled impedance refers to PCB traces manufactured to achieve a specific characteristic impedance within a defined tolerance (typically ±10%). This requires controlling trace width, dielectric thickness, and material Dk with precision. Fabricators adjust trace widths during CAM to compensate for etch variations. Test coupons with TDR (time domain reflectometry) measurement verify impedance on production panels. Controlled impedance is essential for high-speed digital, RF, and any signal where reflections would cause errors.

### copper pour

Copper pour (or copper fill) floods unused areas of a PCB layer with copper, typically connected to ground or power nets. Benefits include lower impedance for power distribution, improved thermal dissipation, reduced EMI (ground pours shield signals), and more even copper distribution for manufacturing (prevents warping, improves etching uniformity). Design considerations: set appropriate clearance to other nets (typically 0.2-0.3mm), use thermal relief connections to pads for solderability, and avoid isolated copper islands that can cause antenna effects. For RF designs, continuous ground pours under signal traces are essential for controlled impedance.

### creepage

Creepage is the shortest path between two conductive parts measured along the surface of the insulating material, as opposed to clearance which is the straight-line distance through air. If two pads are separated by a slot, the clearance might be 2 mm across the gap, but the creepage follows down one side and up the other - potentially much longer. This distinction matters because contamination, humidity, and dust can create leakage paths along surfaces that wouldn't arc through air. Dirty or damp insulator surfaces become slightly conductive, allowing tracking currents. IPC-2221 and safety standards (IEC 60950/62368) specify minimum creepage distances based on working voltage, pollution degree (environmental contamination level), and material group (tracking resistance of the laminate). Conformal coating can effectively increase creepage by providing a clean, hydrophobic barrier over the PCB surface.

### decoupling

Decoupling provides local charge storage near IC power pins to supply transient current demands faster than the power supply can respond. Decoupling capacitors filter high-frequency noise and maintain stable voltage during load switching. Effective decoupling requires capacitors with low ESL (equivalent series inductance), short trace lengths to component, and a hierarchy of values covering different frequency ranges. Embedded capacitance provides decoupling at frequencies where discrete capacitors become ineffective (typically above 100-500 MHz).

### design rules

Design rules are manufacturing constraints that CAD tools check during layout: minimum trace width, spacing, annular ring, drill sizes, etc. Rules vary by manufacturer capability - standard PCB shops might require 0.15mm trace/space while HDI specialists achieve 0.075mm. Design Rule Check (DRC) flags violations before fabrication. Rules also encode electrical requirements: controlled impedance traces, differential pair spacing, high-voltage clearance. Getting design rules from your fabricator early prevents redesigns. Violating design rules increases cost, reduces yield, or makes the design unfabricable.

### DFM

Design for Manufacturability (DFM) means designing your PCB so it can be built reliably without special processing. Key DFM guidelines: use 6 mil (150µm) trace/space instead of 3 mil unless density requires it, specify 0.3mm drill sizes instead of 0.2mm where possible, maintain 6 mil annular rings, avoid acid traps (acute angles <90° where etchant pools), and keep 5 mil solder mask dams between pads. Following DFM rules reduces cost by 10-30% and improves yields. Request your fabricator's DFM guidelines before finalizing your design.

### escape routing

Escape routing is the technique of routing signals from component pads (especially BGAs) to via fanouts or trace channels. For large BGAs, inner rows cannot reach the perimeter directly and must escape through vias to inner layers. Fine-pitch BGAs (<0.8mm) require micro-vias and via-in-pad for escape routing. The number of layers needed depends on BGA pitch, pad count, and via/trace technology. Via-in-pad allows one trace per row per layer to escape. Dog-bone fanout requires space between pads, limiting use at fine pitches.

### fanout

Fanout refers to the via pattern and trace routing that connects surface component pads to vias for escape routing to other layers. Dog-bone fanout uses short traces from pads to via lands between pads, suitable for >0.8mm pitch. Via-in-pad places vias directly in the pad, required for fine pitch. Fanout strategy affects routing density, layer count, and cost. Good fanout balances via count, layer usage, and signal integrity. Complex BGAs may use multiple fanout strategies for different regions.

### ferrite bead

Ferrite beads suppress high-frequency noise on PCB power rails and I/O lines. Unlike inductors that store energy, ferrite beads dissipate noise as heat. On PCB power distribution, place ferrite beads after bulk capacitors and before the load to isolate noisy digital circuits from sensitive analog sections. Specify by impedance at 100 MHz (common ratings: 30Ω, 120Ω, 600Ω) and DC current rating. Package size (0402, 0603, 0805) affects current capacity and self-resonant frequency. For designs requiring EMI compliance, ferrite beads on I/O lines near connectors are often necessary to meet radiated emission limits.

### footprint

A footprint (or land pattern) defines the copper pads, solder mask openings, and silkscreen markings needed to mount a specific component package on a PCB. Footprints must match the component's lead pitch, pad dimensions, and overall package size. IPC-7351 provides standardized footprint dimensions for common packages. Footprints include three density levels: most (largest pads, easiest assembly), nominal, and least (smallest pads, highest density). For new components, obtain recommended footprints from manufacturer datasheets or use IPC calculators. Incorrect footprints cause assembly defects: too small leads to weak joints, too large causes bridges.

### Gerber

Gerber is the industry-standard file format for PCB manufacturing, defining the artwork for each layer. Named after Gerber Scientific (now Ucamco), the format uses RS-274X (extended Gerber) or the newer Gerber X2 with embedded metadata. A complete Gerber package includes files for each copper layer, solder mask, silkscreen, paste stencil, and board outline. Excellon format is used for drill files. ODB++ is an alternative single-file format containing all manufacturing data.

### high-speed

High-speed design refers to signals where transmission line effects become significant - typically rise times under 1ns or frequencies above 100MHz. At these speeds, trace geometry affects impedance, vias add inductance, and return paths matter. Key concerns: controlled impedance, length matching for differential pairs, via stub resonance, crosstalk, and power delivery network impedance. Materials matter too - lower Dk means faster propagation, lower Df means less loss. PCIe, DDR4/5, USB3, and Ethernet all require high-speed design practices. Simulation (IBIS, S-parameters) validates designs before fabrication.

### layer count

Layer count is the total number of copper layers in a multilayer PCB. Boards range from single-sided (1 layer), double-sided (2 layers), to multilayer (4, 6, 8... up to 50+ layers). More layers provide more routing channels, dedicated ground/power planes, and support for fine-pitch BGAs, but increase cost and complexity. Layer count affects stackup design, drilling strategy, and manufacturing process selection. High-layer-count boards (>20 layers) require sequential lamination and careful registration.

### microwave

Microwave frequencies range from approximately 300 MHz to 300 GHz, with wavelengths from 1 meter to 1 millimeter. At microwave frequencies, PCB traces behave as transmission lines where impedance, loss, and phase are critical. Microwave PCBs typically use low-loss materials like Rogers or Taconic PTFE-based laminates with tight Dk tolerance. Applications include radar, satellite communications, cellular base stations, and automotive radar (77 GHz). Microwave design considers waveguides, transitions, and antenna integration. Material selection balances electrical performance with processability and cost.

### ODB++

ODB++ is a comprehensive PCB manufacturing data format developed by Mentor (now Siemens) that contains all information needed for fabrication and assembly in a single structured package. Unlike Gerber (separate files for each layer), ODB++ includes layer data, drill files, netlist, component placement, design rules, and metadata. ODB++ enables automated DFM checks, intelligent panelization, and assembly programming. It's the native format for some CAM systems. IPC-2581 is a similar open-standard alternative.

### PDN

Power Distribution Network (PDN) encompasses all elements delivering power from the supply to IC power pins: PCB power/ground planes, decoupling capacitors, VRMs (voltage regulator modules), and interconnecting traces and vias. PDN impedance must remain below a target value (Ztarget = ripple voltage tolerance / transient current) across all frequencies of interest. PDN analysis evaluates plane resonances, capacitor effectiveness, via inductance, and overall impedance profile. Poor PDN causes voltage droop, increased noise, and signal integrity problems.

### pitch

Pitch is the center-to-center distance between adjacent leads or pads. Standard through-hole: 2.54mm (0.1 inch). Fine-pitch SMT: 0.5mm, 0.4mm. Ultra-fine BGA: 0.3mm, 0.25mm. Smaller pitch increases density but challenges manufacturing - finer stencil apertures, tighter placement accuracy, smaller vias for escape routing. 0.4mm BGA pitch typically requires HDI (micro-vias). Below 0.3mm pitch may need advanced packaging (interposers, embedded die). Component pitch determines PCB technology requirements and assembly capability. Verify your assembler can handle the pitch before selecting components.

### RF

Radio Frequency (RF) refers to electromagnetic signals in the frequency range of approximately 3 kHz to 300 GHz. RF PCB design requires controlled impedance transmission lines, low-loss materials (PTFE, Rogers, high-frequency laminates), careful ground plane design, and attention to electromagnetic coupling. As frequency increases, wavelength decreases, making PCB features electrically significant (a trace stub becomes a resonator). RF circuits include filters, amplifiers, mixers, and antennas. Millimeter-wave applications (>30 GHz) demand the tightest material and fabrication tolerances.

### routing

Routing is the process of creating copper traces that connect component pins according to the schematic netlist. Manual routing gives full control for critical signals; auto-routing handles bulk connections. Key considerations: signal integrity (controlled impedance, length matching), power delivery (wide traces, multiple vias), manufacturability (minimum trace/space, acid traps), and EMI (return paths, shielding). Route critical signals first - clocks, high-speed differentials, power. Layer assignment affects crosstalk and impedance. Good routing is the difference between a working board and EMI failures.

### shielding

EMI shielding uses conductive barriers to contain or exclude electromagnetic fields. PCB-level shielding includes: ground planes (blocks E-fields), edge plating (creates Faraday cage), embedded shields (copper pours around sensitive circuits), and shield cans (metal covers over RF sections). Effectiveness depends on material conductivity, aperture size (keep below λ/20), and ground continuity. Shielding prevents both emission (failing FCC/CE) and susceptibility (interference from external sources). RF circuits require careful shielding design - slots in ground planes act as slot antennas.

### spacing

Spacing (or clearance) is the minimum distance between copper features - trace to trace, trace to pad, pad to plane edge. Manufacturing capability sets the floor: standard is 0.15mm (6 mil), advanced is 0.1mm (4 mil), HDI can achieve 0.075mm (3 mil). Voltage requirements often demand more: IPC-2221 specifies spacing based on voltage and coating. At 100V, uncoated internal layers need 0.25mm minimum. High-voltage designs (>500V) may need 2mm+ spacing or slots. Spacing violations cause shorts in manufacturing or arcing in the field. DRC catches spacing errors.

### stackup

Stackup defines the layer arrangement in a multilayer PCB: the sequence of signal, ground, and power layers; the materials (core and prepreg types); dielectric thicknesses; and copper weights. A well-designed stackup ensures impedance control, minimizes crosstalk, provides adequate power distribution, and meets mechanical requirements. Symmetric stackups (mirrored around the center) minimize warpage. The stackup must be manufacturable with standard material combinations and validated for the target impedances.

### termination

Termination provides impedance matching at the end of a transmission line to absorb signal energy and prevent reflections. Series termination places a resistor at the source, matching driver output impedance to the line. Parallel termination places a resistor at the receiver equal to line impedance. AC termination uses capacitor in series with resistor to reduce DC power. On PCBs, termination resistors are typically discrete SMD components (0402 or 0603). For tight tolerances, specify 1% resistors. Embedded resistors in the PCB stackup offer shorter interconnects and save board space for high-speed applications.

### thermal management

High-power components require heat dissipation paths designed into the PCB. Effective strategies include: thermal via arrays under QFNs and BGAs (0.3mm vias on 0.6mm pitch reduce junction temperature by 20-40°C), 2oz copper planes that spread heat 50% more effectively than 1oz, and metal-core substrates for LED and power applications. When designing for thermal performance, specify heavy copper (2-4 oz) on inner layers connecting to thermal pads. For extreme cases (>5W per component), consider aluminum-backed or copper-core PCBs. Thermal simulation before fabrication identifies hot spots that can cause field failures.

### trace width

Trace width determines both current-carrying capacity and characteristic impedance. For current: 1oz copper at 10°C rise carries roughly 1A per 0.25mm width on outer layers, half that for inner layers. IPC-2152 provides detailed calculations. For impedance: wider traces have lower impedance - a 50Ω microstrip on FR-4 might be 0.2mm wide over a 0.1mm dielectric. Minimum trace width depends on manufacturing capability: 0.15mm standard, 0.1mm advanced, 0.075mm HDI. Trace width affects routing density, thermal performance, and signal integrity.



================================================================================

# Technical Library

17 articles on PCB design and manufacturing.

## Index

- [BGA Component Design Guide](#bga-component-facts)
- [Castellated Holes and Edge Plating](#castellated-holes-edge-plating)
- [Controlled Impedance PCB Design](#controlled-impedance-pcb-design)
- [Embedded Capacitance Layers in PCBs](#embedded-capacitance-layers)
- [Embedded Capacitors in PCBs](#embedded-capacitors)
- [Embedded Components in PCBs](#embedded-components-overview)
- [Embedded Resistors in PCBs](#embedded-resistors)
- [Planar Transformers in PCBs](#embedded-transformers)
- [Flex PCB Capability Limits](#flex-pcb-capability-limits)
- [How Multilayer PCBs Are Made: Step-by-Step Fabrication Guide](#how-to-build-pcbs)
- [Micro-Via Advantages in PCBs](#micro-via-advantages)
- [Multilayer PCB Capabilities](#pcb-capability-limits)
- [PCB Component Cooling with Thermal Vias](#pcb-component-cooling)
- [PCB Materials and Laminates Guide](#pcb-materials-guide)
- [RF and Microwave PCB Substrate Selection Guide](#rf-microwave-substrate-selection)
- [The Impact of RoHS on PCBs and Other Components](#rohs-effect-on-pcbs)
- [Solder Mask and Via Types](#solder-mask-via-types)

---

<a id="bga-component-facts"></a>

## BGA Component Design Guide

## The Challenge: Routing High-Pin-Count Packages

Ball Grid Array (BGA) packages pack hundreds or thousands of connections into a small footprint. Unlike peripheral-leaded packages, BGA balls are arranged in a grid across the entire package bottom—which creates a routing challenge. You can't simply run traces to the edge; you need to escape signals from under the package through multiple PCB layers.

Getting BGA routing right requires understanding pad geometry, via placement, and solder mask rules. Get it wrong and you'll face assembly defects, signal integrity problems, or designs that simply can't be manufactured.

## BGA Package Structure

![Cross-sectional diagram of a flip chip BGA package showing the die, substrate, solder balls, and underfill layers](/assets/images/technical-library/screenshot-bga-package.webp)

*Flip chip BGA cross-section: die attached to substrate with solder balls forming the external connections*

The BGA substrate routes signals from the die to the ball grid. Understanding this structure helps when debugging assembly issues or specifying package requirements.

For detailed BGA specifications, see the [Texas Instruments BGA Application Guide](/assets/pdfs/bga-texas-instruments-spru811a.pdf) (PDF).

## Orientation and Placement

![Diagram showing BGA chip orientation markings and pin A1 location identification](/assets/images/technical-library/bild13.webp)

*BGA orientation: pin A1 location must be clearly marked in your assembly drawing*

## Fanout Strategies

The key to BGA routing is the fanout pattern—how you escape signals from the ball grid to the routing layers beneath.

### Dog-Bone Fanout

![Dog-bone via fanout pattern for BGA routing showing via placement between pads](/assets/images/technical-library/bga5.webp)

*Dog-bone pattern: via placed adjacent to pad, connected by short trace*

This is the most common approach for larger pitch BGAs (0.8 mm and above). Each pad connects to a via placed in the gap between pads.

### Via-in-Pad

![Via-in-pad routing pattern showing via placed directly in the BGA pad](/assets/images/technical-library/bga6.webp)

*Via-in-pad: via drilled directly through the pad centre*

For fine-pitch BGAs (0.5 mm and below), there's no room for dog-bone fanout. The via must be placed directly in the pad, filled with conductive or non-conductive material, and planarised for reliable solder joints.

### Layer Escape Patterns

![BGA layer escape diagram showing signals routed to different layers](/assets/images/technical-library/bga7.webp)

*Layer escape: outer rows exit on layer 1, inner rows drop to layers 2, 3, and beyond*

![Alternative BGA escape pattern with staggered via placement](/assets/images/technical-library/bga8.webp)

*Staggered escape pattern for dense BGAs*

![Complex BGA fanout showing multiple layer transitions](/assets/images/technical-library/bga9.webp)

*High-density BGA requiring four or more routing layers for full escape*

## Solder Mask Considerations

![Solder mask edge diagram showing clearance requirements around BGA pads](/assets/images/technical-library/bga14.webp)

*Solder mask to pad clearance: minimum 2 mil (0.05 mm) per side typical*

### Solder Mask Defined (SMD) vs Non-Solder Mask Defined (NSMD)

**NSMD pads** (most common):
- Solder mask opening is larger than the copper pad
- Better solder joint reliability—fillet forms around pad edge
- Preferred for most BGA applications

**SMD pads**:
- Solder mask overlaps the pad edge
- Tighter pitch capability—mask controls pad spacing
- Used when NSMD clearances can't be achieved

## Pad Size and Via Geometry

### Design Parameters by Ball Pitch

All dimensions in mm:

| Ball Pitch | 1.50 | 1.27 | 1.0 | 0.80 | 0.65 | 0.50 |
|------------|------|------|-----|------|------|------|
| Solder Ball Diameter | 0.75 | 0.75 | 0.60 | 0.50 | 0.40 | 0.30 |
| Solder Pad Diameter | 0.50 | 0.50 | 0.40 | 0.35 | 0.30 | 0.25 |
| PTH Diameter | 0.30 | 0.30 | 0.20 | 0.20 | 0.20 | 0.15 |
| PTH Pad Diameter | 0.50 | 0.50 | 0.40 | 0.40 | 0.40 | 0.40 |
| Line Width (1 line/channel) | 0.30 | 0.25 | 0.20 | 0.125 | 0.075 | 0.075 |
| Line Width (2 lines/channel) | 0.20 | 0.15 | 0.12 | 0.075 | 0.050 | 0.050 |

### Column Grid Array Routing Guidelines

Column Grid Arrays (CGAs) use solder columns instead of balls for better thermal cycling reliability. The table below shows routing parameters for standard (left columns) and fine-feature (right columns) PCB processes:

All dimensions in mm:

| Contact Pitch | 1.0 | 1.25 | 1.5 | 1.0 | 1.25 | 1.5 |
|---------------|-----|------|-----|-----|------|-----|
| | *Standard process* ||| *Fine-feature process* |||
| Contact Land | 0.55 | 0.65 | 0.75 | 0.55 | 0.65 | 0.75 |
| Via Land | 0.61 | 0.61 | 0.61 | 0.50 | 0.50 | 0.50 |
| Via Hole | 0.33 | 0.33 | 0.33 | 0.25 | 0.25 | 0.25 |
| Annular Ring | 0.14 | 0.14 | 0.14 | 0.12 | 0.12 | 0.12 |
| Signal Line | 0.13 | 0.13 | 0.13 | 0.10 | 0.10 | 0.10 |
| Air Gap | 0.13 | 0.13 | 0.13 | 0.10 | 0.10 | 0.10 |
| Signal Tracks | 1 | 2 | 3 | 1 | 2 | 3 |

### Stencil and Pad Specifications for Assembly

Solder paste stencil thickness and aperture sizing affect solder joint quality. These guidelines apply to BGA and related area-array packages:

| Component Type | Stencil Foil (mm) | Aperture Size | Board Pad |
|----------------|-------------------|---------------|-----------|
| CBGA (Ceramic BGA) | 0.20 | 0.79 round | 0.71 round |
| TBGA (Tape BGA) | 0.18 | 0.81 round | 0.66 round |
| PBGA (Plastic BGA) | 0.20 | 0.79 round | 0.71 round |
| CSP (Chip Scale Package) | 0.13 | 0.36 round | 0.30 round |

### Design Rules by Pitch

| BGA Pitch | Pad Diameter | Via Size | Trace Width | Routing Layers |
|-----------|--------------|----------|-------------|----------------|
| 1.27 mm | 0.6 mm | 0.3 mm PTH | 6 mil | 2 (dog-bone) |
| 1.0 mm | 0.5 mm | 0.25 mm PTH | 5 mil | 2–4 |
| 0.8 mm | 0.4 mm | 0.2 mm PTH | 4 mil | 4 |
| 0.65 mm | 0.3 mm | 0.15 mm PTH | 3.5 mil | 4–6 |
| 0.5 mm | 0.25 mm | 0.1 mm laser | 3 mil | 6+ (HDI) |
| 0.4 mm | 0.2 mm | 0.1 mm laser | 2.5 mil | 6+ (HDI) |

## Real-World Examples

These examples show typical design parameters for production BGAs at different densities.

### 313-Ball BGA (1.8 mm pitch)

A large-pitch BGA routable with standard PCB processes. The wide pitch allows generous pad sizes and conventional PTH vias—no HDI required.

| Parameter | Value |
|-----------|-------|
| Contacts | 313 |
| Pitch | 1.8 mm |
| Pad | 0.75 mm |
| Line/space | 0.15 mm |
| Vias | 0.4 mm |
| Mask opening | 0.55 mm |

### 64-Ball BGA (0.8 mm pitch)

A mid-density BGA at the boundary between standard and HDI technology. Dog-bone fanout is possible but tight; micro-vias provide additional escape options.

![Routed BGA breakout pattern showing actual trace routing from 64-ball BGA](/assets/images/technical-library/picture35.webp)

*Production BGA fanout with dog-bone via pattern*

| Parameter | Value |
|-----------|-------|
| Contacts | 64 |
| Pitch | 0.8 mm |
| Pad | 0.3 mm |
| Line/space | 0.15 mm |
| Vias | 0.3 mm |
| Micro-vias | 0.1 mm |

## When HDI Is Required

Standard through-hole technology works for BGAs down to about 0.65 mm pitch. Below that, you'll typically need [HDI with micro-vias](/technical-library/micro-via-advantages/):

- **0.5 mm pitch**: Usually requires 1+N+1 HDI
- **0.4 mm pitch**: Often requires 2+N+2 HDI or any-layer
- **Sub-0.4 mm**: Almost always any-layer HDI

---

## Related Articles

- [Micro-Via Advantages in PCBs](/technical-library/micro-via-advantages/) – HDI routing for fine-pitch BGAs
- [Solder Mask and Via Types](/technical-library/solder-mask-via-types/) – Via covering options under BGAs
- [Multilayer PCB Capabilities](/technical-library/pcb-capability-limits/) – BGA pad and routing specifications

---

**Need help with BGA routing?** [Request a quote](/quote/) – our engineers review BGA fanout as part of every technical review.

---

<a id="castellated-holes-edge-plating"></a>

## Castellated Holes and Edge Plating

## The Problem: Making PCBs That Mount Like Components

Sometimes you need a PCB that functions as a component—a module that solders directly onto a host board. Standard PCB edges are bare laminate, with no solderable surface. You could add a connector, but that adds cost, height, and potential failure points.

The solution is castellated holes: plated half-holes at the board edge that provide solderable contact points, allowing one PCB to mount directly onto another.

## What Are Castellated Holes?

Castellated holes are formed by drilling plated through-holes at the board edge, then routing through them to create half-moon shaped contacts. The name comes from castle battlements—the grooved pattern resembles medieval fortifications.

![3D rendering of a planar PCB transformer module with castellated edge contacts, showing the top coil pattern and ferrite core mounting area](/assets/images/technical-library/55fafd11-bu9.webp)

*Planar transformer module with castellated holes for direct board-to-board soldering*

## How Castellation Works

The process requires careful sequencing:

1. **Drill** – Full plated through-holes are drilled at the intended edge locations
2. **Plate** – Holes are copper-plated like standard PTH vias
3. **Route** – The board outline is cut through the centre of the holes, leaving half-cylinders of plated copper at the edge

Castellation is typically applied to specific areas rather than the entire board perimeter. Tabs are needed to hold panels during wet processing—you can't plate an edge that's already been cut.

## Applications

### Wireless Modules
Bluetooth, WiFi, and cellular modules commonly use castellated mounting. The module manufacturer can fully test the PCB, then customers solder it as a single component.

### Daughter Boards
Castellated edges allow vertical or horizontal mounting of small boards without connectors.

### Planar Transformers
[PCB-based transformers](/technical-library/embedded-transformers/) use castellations to connect primary and secondary windings across stacked boards.

### Test Fixtures
Castellated boards can plug into pogo-pin test fixtures for production testing.

## Design Considerations

### Hole Size and Pitch
- **Minimum hole diameter**: 0.6 mm (finished)
- **Minimum pitch**: 1.0 mm (edge-to-edge spacing depends on hole size)
- **Copper thickness**: Standard PTH plating (typically 20–25 µm minimum)

### Board Thickness
Thinner boards (0.4–0.8 mm) are common for castellated modules to minimise the height added to the host assembly.

### Surface Finish
ENIG is preferred for castellated contacts—flat surface, good shelf life, and reliable soldering. HASL can leave uneven surfaces in the half-holes.

## Manufacturing Limits

We regularly produce castellated boards as small as 5×5 mm in 0.4 mm thick FR-4. Smaller is possible but discuss with us first—handling and panelisation become challenging at very small sizes.

---

## Related Articles

- [Embedded Transformers in PCBs](/technical-library/embedded-transformers/) – Planar transformer modules using castellated mounting
- [How Multilayer PCBs Are Made](/technical-library/how-to-build-pcbs/) – Understanding the plating and routing process
- [Multilayer PCB Capabilities](/technical-library/pcb-capability-limits/) – Edge plating specifications

---

**Need castellated PCBs for your module design?** [Request a quote](/quote/) – we supply boards as small as 5×5 mm with castellated edges.

---

<a id="controlled-impedance-pcb-design"></a>

## Controlled Impedance PCB Design

## The Problem: Calculators Don't Match Reality

Every CAD tool and online calculator can estimate trace impedance from geometry. The formulas are mathematically correct. Yet fabricators routinely adjust trace widths from what designers specify - sometimes by 10-20% - to hit the target impedance after manufacturing.

Why the disconnect? Real-world impedance depends on variables that calculators can't fully model:

- **Actual etch profile** - traces aren't rectangular; they're trapezoidal, and the taper varies by copper weight, etch chemistry, and line width
- **Specific prepreg construction** - Dk varies with resin content, glass style, and layer position in the stackup
- **Copper foil type** - RTF, VLP, HVLP each interact differently with the dielectric
- **Process variations** - plating thickness, lamination pressure, material lot differences
- **Solder mask effects** - thickness, Dk, and coverage vary by process

Fabricators account for all this using field-solver software (typically Polar Si9000) calibrated against their actual production data. That's why their calculated widths differ from yours - and why their boards hit the target impedance.

## Evidence From Supplied Boards

Controlled impedance appears in more than 500 projects in our supplied-job records, including builds using named RF laminates and blind or buried vias.

This rounded count is a lower bound because older specifications are incomplete. It demonstrates delivered manufacturing experience, not a promise that every material, tolerance, and stackup combination is interchangeable. We review those requirements together before quoting.

## The Solution: Specify Intent, Not Geometry

The practical workflow for controlled impedance isn't "calculate the trace width yourself." It's:

1. **Specify your target impedance** (50Ω, 100Ω differential, etc.)
2. **Use a recognisable trace width** to flag controlled-impedance nets
3. **Let your fabricator calculate the actual width** for their process

This is how experienced designers work, and it's more reliable than trying to pre-calculate widths that will be changed anyway.

### What to Include in Your Design Package

When you need controlled impedance, provide:

| Information | Example | Why It Matters |
|-------------|---------|----------------|
| Target impedance | 50Ω ±10% | The actual requirement |
| Tolerance | ±10% (standard) or ±5% (tight) | Affects cost and process |
| Layer(s) | Layer 1 microstrip, Layer 3 stripline | Different structures = different widths |
| Differential pairs | 100Ω diff on USB, 90Ω on Ethernet | Pair identification |
| Reference plane | Ground on Layer 2 | Defines the structure |
| Trace identifier | Unique width (e.g., 6 mil for 50Ω nets) | Helps fab identify controlled nets |

### Using Trace Width as a Flag

A practical technique: use a distinctive trace width for each impedance class, even if it's not the final manufactured width. This makes controlled-impedance nets easy to identify in Gerber review.

For example:
- 6 mil width = 50Ω single-ended nets
- 5 mil width = 100Ω differential pairs
- 8 mil width = 40Ω DDR nets

Your fabricator will adjust these widths to achieve the target impedance on their process. The distinctive width just makes the nets identifiable.

## Impedance Structures

### Microstrip (Outer Layers)

A trace on an outer layer with a reference plane below. Part of the electromagnetic field travels through air (or solder mask), so the effective dielectric constant is lower than the bulk material.

**Characteristics:**
- Easier to probe and test
- More susceptible to EMI
- Solder mask affects impedance (typically -1 to -2Ω)
- Wider traces than stripline for same impedance

### Stripline (Inner Layers)

A trace sandwiched between two reference planes, fully embedded in dielectric. More predictable impedance because the field is entirely within the laminate.

**Characteristics:**
- Better shielding from external noise
- Lower crosstalk between adjacent traces
- Tighter impedance tolerance achievable
- Narrower traces than microstrip for same impedance

### Edge-Coupled Differential

Two traces routed in parallel with controlled spacing. The coupling between traces creates odd-mode and even-mode impedances; differential impedance is twice the odd-mode.

**Key parameter:** Spacing between traces affects coupling and differential impedance. Closer spacing = lower differential impedance.

## Common Impedance Targets

| Application | Single-Ended | Differential | Typical Tolerance |
|-------------|--------------|--------------|-------------------|
| General digital | 50Ω | 100Ω | ±10% |
| USB 2.0 | 45Ω | 90Ω | ±10% |
| USB 3.x | N/A | 90Ω | ±10% |
| HDMI | N/A | 100Ω | ±15% |
| PCIe | N/A | 85Ω | ±15% |
| DDR4/5 | 40Ω | 80Ω | ±10% |
| Ethernet | N/A | 100Ω | ±10% |
| LVDS | N/A | 100Ω | ±10% |

## What Affects Impedance

Understanding what drives impedance helps you make good design decisions, even if you're not calculating exact widths.

### Trace Width
Wider traces = lower impedance. This is the primary variable fabricators adjust.

### Dielectric Thickness
Thinner dielectric (trace closer to reference plane) = lower impedance. This is set by your stackup choice.

### Dielectric Constant (Dk)
Higher Dk = lower impedance. FR-4 is typically 4.2-4.5; high-speed laminates range from 3.0-3.8.

### Copper Thickness
Thicker copper = slightly lower impedance. Minor effect compared to width and height.

### Differential Spacing
Closer spacing = stronger coupling = lower differential impedance. Trade-off with crosstalk and manufacturing capability.

## What We Do With Your Impedance Requirements

When you order controlled-impedance boards, here's what happens:

1. **Stackup proposal** - We propose layer thicknesses and materials based on your requirements
2. **Impedance modelling** - Field solver (Polar Si9000 or similar) calculates required trace widths using actual material data from the production facility
3. **Width adjustment** - Your trace widths are modified to hit target impedance
4. **Test coupon** - Impedance test structures added to the panel
5. **TDR verification** - Time Domain Reflectometry confirms actual impedance after manufacturing

This is why we ask for your impedance requirements, not your calculated widths. We need to run calculations using the actual process data from the facility building your boards.

### What You'll Receive

On controlled-impedance jobs, we provide:
- **Stackup drawing** with actual layer thicknesses and materials
- **Impedance report** showing calculated values for each structure
- **TDR test results** from production panels (if specified)

## Design Guidelines

### Reference Planes

Every controlled-impedance trace needs a solid, uninterrupted reference plane. Breaks in the plane (slots, splits, via clearances) create impedance discontinuities.

**Best practice:** Avoid routing controlled-impedance traces over plane splits. If you must cross a split, use stitching capacitors or route on a different layer.

### Via Transitions

Vias add inductance and can disrupt impedance. For high-speed signals:
- Use back-drilled or blind vias to reduce stub length
- Place ground vias near signal vias for return path
- Keep via runs short

### Length Matching

For differential pairs and parallel buses, match trace lengths to control timing skew. Your fabricator doesn't adjust for length - that's your responsibility.

### Tolerance Selection

**±10%** is standard and achievable with normal processes. Suitable for most digital interfaces including USB, PCIe, and Ethernet.

**±5%** requires tighter process control and often inner-layer routing. Costs more. Usually only needed for very high-speed serial links or RF applications.

## Working with Shipco

Here's how controlled impedance jobs flow through us:

1. **Send your requirements** - target impedances, tolerances, layer assignments
2. **Factory proposes a stackup** - materials and thicknesses to meet your targets, modelled using Polar Si9000 or equivalent
3. **Review and approval** - you confirm the stackup works for your design
4. **Production** - boards manufactured with impedance test coupons (if requested)
5. **Verification** - TDR testing confirms compliance (if requested)

We coordinate this process and review the stackup proposals, but the impedance modelling is done by the production facility using their actual material data.

### Controlled Impedance Checklist

If your design requires controlled impedance, include the following with your quote request:

**Required:**
- [ ] Target impedance values (e.g., 50Ω single-ended, 100Ω differential)
- [ ] Tolerance requirements (±10% standard, ±5% if needed)
- [ ] Which layers/nets require impedance control

**If applicable:**
- [ ] Stackup preference or constraints
- [ ] Reference plane assignments (which layer is the return path)
- [ ] Dielectric material preference (standard FR-4, high-speed, RF)
- [ ] Differential pair spacing requirements
- [ ] Thickness constraints (overall board thickness, flex areas)
- [ ] TDR test coupon and report required

**We'll handle:**
- Trace width calculations using actual material data
- Stackup optimization to meet your targets
- Test coupon design and placement (if requested)
- TDR verification and reporting (if requested)

Missing something from the list? No problem - we'll ask during technical review. But providing this information upfront speeds up the quoting process.

---

## Frequently Asked Questions

### Why does my fabricator change my trace widths?

Your calculated widths are based on nominal material properties. Fabricators recalculate using their actual process data - specific prepreg Dk values, measured etch profiles, copper foil characteristics. Their adjusted widths hit the target impedance after manufacturing; your calculated widths likely wouldn't.

### Should I use an impedance calculator?

Calculators are useful for understanding relationships (wider = lower impedance, thinner dielectric = lower impedance) and for initial stackup feasibility checks. But don't expect calculator results to match production. For final trace widths, rely on your fabricator's field-solver calculations.

### What tolerance should I specify?

±10% for most applications. This is achievable with standard processes and is sufficient for USB, PCIe, Ethernet, DDR, and most high-speed digital. Specify ±5% only when your signal integrity analysis shows you genuinely need it - tighter tolerance costs more and may limit supplier options.

### Microstrip or stripline?

**Microstrip** (outer layer) when you need easy probing, have EMI-tolerant signals, or want simpler stackups. **Stripline** (inner layer) when you need better shielding, lower crosstalk, or tighter impedance control. Many designs use both - stripline for sensitive high-speed signals, microstrip for less critical nets.

### What is differential impedance?

The impedance seen by a differential signal travelling on a coupled pair of traces. It equals twice the odd-mode impedance. Common targets: 90Ω for USB, 100Ω for Ethernet and LVDS, 85Ω for PCIe.

### How is impedance verified?

Time Domain Reflectometry (TDR) measures actual impedance by sending a fast-rise pulse down the trace and analysing reflections. Industry-standard equipment like the Tektronix DSA8300 series achieves sub-millimetre spatial resolution. Fabricators measure dedicated test coupons that replicate your controlled-impedance structures - same layer, trace width, stackup, and reference plane. TDR results appear in the impedance test report delivered with your boards.

### Where are test coupons located?

Most commonly in panel margins - these share identical process conditions with your boards and are discarded at depaneling. Some designs use breakaway tabs that stay attached until you remove them. Physical coupons are delivered on request (for incoming QC or audit), but standard practice is fabricator retains coupons, measures them, and provides the test report.

---

## Related Articles

- [RF and Microwave PCB Fabrication](/rf-microwave-pcb-fabrication/) - Controlled-impedance RF builds and delivered evidence
- [PCB Materials and Laminates Guide](/technical-library/pcb-materials-guide/) - Dielectric constants for different materials
- [RF and Microwave Substrate Selection](/technical-library/rf-microwave-substrate-selection/) - Material selection for high-frequency designs
- [Micro-Via Advantages in PCBs](/technical-library/micro-via-advantages/) - HDI structures for high-speed routing

---

**Need controlled-impedance PCBs?** [Request a quote](/quote/) - we calculate impedance, propose stackups, and verify results as part of our technical review.

---

<a id="embedded-capacitance-layers"></a>

## Embedded Capacitance Layers in PCBs

> **Archive Note:** Embedded capacitance layer technology using thin high-Dk dielectrics is technically viable, but supplier availability remains limited. Materials like DuPont Interra and 3M ECM exist, but finding PCB manufacturers with qualified processes requires effort. This article explains the technology for educational purposes.

## The Problem: Decoupling Fails at High Frequencies

Discrete surface-mount capacitors work well for decoupling at moderate frequencies, but above 1 GHz they become ineffective. The culprit is parasitic inductance - the capacitor's leads, solder joints, and PCB traces all add inductance that dominates at high frequencies, turning your decoupling capacitor into an inductor precisely when you need it most.

For high-speed digital designs, RF circuits, and power-integrity-critical applications, this creates a real problem: how do you provide low-impedance decoupling at frequencies where discrete components fail?

## The Solution: Embed Capacitance in the Stackup

By forming capacitance directly within the PCB layer structure, you eliminate the parasitic inductance of discrete components entirely. A thin dielectric layer (typically 12 µm) sandwiched between copper planes creates distributed capacitance across the entire power plane area.

**Key benefits:**

- Effective decoupling above 1 GHz where discretes fail
- Minimal ESR and virtually zero lead inductance
- Reduced power bus noise and radiated emissions
- Smaller package size - fewer surface-mount components needed
- Built-in decoupling that doesn't consume board space

A complete embedded capacitance stackup can be built below 0.35 mm thick, using three 50 µm prepreg layers, two 12 µm capacitance dielectrics, and 18 µm copper foil.

### Dielectric Material Options

DuPont and 3M both offer high-capacitance dielectric laminates designed for this application:

- [Interra™ HK 04J Planar Capacitor Laminate](http://www.dupont.com/products-and-services/electronic-electrical-materials/printed-circuit-board-materials/brands/interra-thin-copper-clad-laminates/products/interra-planar-capacitor-laminate.html) (DuPont)
- [3M Embedded Capacitance Material (ECM)](https://www.3m.com/3M/en_US/company-us/all-3m-products/~/All-3M-Products/Electronics/Data-Center/Electronics-Materials/Interconnect-Solutions/Embedded-Capacitance-Material/?N=5002385+8709318+8709343+8710652+8711017+8734573+8743710+3294857497&rt=r3)

## Example Stackup: Embedded Capacitance with Blind Vias

![Cross-section diagram showing a multilayer PCB stackup with two embedded capacitance layers (12 µm each) connected via blind vias, with copper planes, core, and prepreg layers labelled](/assets/images/technical-library/3ab7bc21-capacitance_layer_blind_via_shipco.webp)

*Multilayer stackup with embedded capacitance layers accessed through blind vias*

This configuration uses blind vias to connect surface components directly to the embedded capacitance planes, minimising the inductance path.

### Layer Composition

| Layer | Thickness |
|-------|-----------|
| Final plating | 18 µm |
| Second plating | 18 µm |
| Base copper | 18 µm |
| Core | 100 µm |
| Base copper | 18 µm |
| **Capacitance layer** | **12 µm** |
| Base copper | 18 µm |
| Second plating | 18 µm |
| Prepreg | 100 µm |
| Second plating | 18 µm |
| Base copper | 18 µm |
| **Capacitance layer** | **12 µm** |
| Base copper | 18 µm |
| Core | 100 µm |
| Base copper | 18 µm |
| Second plating | 18 µm |
| Final plating | 18 µm |

**Total thickness: 0.44 mm**

## Example Stackup: Embedded Capacitance Without Blind Vias

![Cross-section diagram showing a simpler multilayer PCB stackup with two embedded capacitance layers forming distributed power planes, without blind via connections](/assets/images/technical-library/3f565f17-capacitance_layer_no_blind_via_shipco.webp)

*Simpler stackup using embedded capacitance as distributed power planes*

This approach treats the capacitance layers as distributed power planes rather than point connections. In the example shown:

- Plane A connects to −12 V
- Plane C connects to +5 V
- Plane B is isolated (signal reference or unused)

### Layer Composition

| Layer | Thickness |
|-------|-----------|
| Final plating | 18 µm |
| Base copper | 18 µm |
| Core | 100 µm |
| Base copper | 18 µm |
| **Capacitance layer** | **12 µm** |
| Base copper | 18 µm |
| Prepreg | 100 µm |
| Base copper | 18 µm |
| **Capacitance layer** | **12 µm** |
| Base copper | 18 µm |
| Core | 100 µm |
| Base copper | 18 µm |
| Final plating | 18 µm |

**Total thickness: 0.368 mm**

## When to Consider Embedded Capacitance

This technology addresses real problems when:

- Your design operates above 500 MHz and discrete decoupling isn't cutting it
- Power integrity analysis shows impedance problems in the GHz range
- Board space is constrained and you need to reduce component count
- EMI/EMC compliance is challenging due to power bus noise

---

## Industry Status

Embedded capacitance layer technology requires specialized materials and fabrication processes that are not universally available. The challenges include:

- **Material sourcing** - high-Dk thin dielectrics are specialty products
- **Process qualification** - handling ultra-thin layers requires specific equipment and expertise
- **Lead times** - expect longer procurement cycles for non-standard materials
- **Cost** - premium over standard FR-4 stackups

This technology sees use in high-reliability applications (aerospace, defense, medical) where the performance benefits justify the complexity and cost.

---

## Related Articles

- [Embedded Capacitors in PCBs](/technical-library/embedded-capacitors/) - Discrete capacitor embedding techniques
- [Embedded Components Overview](/technical-library/embedded-components-overview/) - Active component embedding technology
- [PCB Materials and Laminates Guide](/technical-library/pcb-materials-guide/) - Dielectric material specifications

---

## Questions?

If you're evaluating embedded capacitance layers for a specific application, [contact us](/contact/). We can discuss the technology and help you understand whether it makes sense for your requirements.

---

<a id="embedded-capacitors"></a>

## Embedded Capacitors in PCBs

> **Archive Note:** Embedded capacitor technology is used in production for specialized applications, but the supplier base remains limited. High-Dk materials from companies like DuPont and Oak-Mitsui exist, but not all PCB manufacturers have qualified processes. This article explains the technology for educational purposes.

## The Problem: Discrete Capacitors Consume Board Space

Surface-mount capacitors take up valuable real estate on crowded boards. In high-density designs, especially under BGAs where you need local decoupling, there's often no room for the dozens of capacitors required.

Embedded capacitors solve this by forming capacitance within the PCB layers themselves, freeing surface area for active components.

## How Embedded Capacitors Work

A capacitor is simply two conductors separated by a dielectric. In a PCB, you can form capacitors using:

- **Thin dielectric layers** (12–25 µm) between copper planes
- **High-Dk materials** that provide more capacitance per unit area
- **Defined copper pads** on adjacent layers

The capacitance formula: **C = ε₀ × εᵣ × A / t**

Where:
- **C** = Capacitance (Farads)
- **ε₀** = Permittivity of free space (8.85 × 10⁻¹² F/m)
- **εᵣ** = Dielectric constant of the material
- **A** = Overlap area of the conductors
- **t** = Dielectric thickness

Because capacitance scales with area and inversely with thickness, embedded capacitors are best suited for smaller values, typically picofarads to low nanofarads.

## Materials

Several manufacturers offer high-Dk laminates specifically designed for embedded capacitance:

| Material | Manufacturer | Dk | Typical Thickness |
|----------|--------------|-----|-------------------|
| BC2000 | Hadco/Sanmina | ~17 | 4–12 µm |
| Interra HK | DuPont | ~10–20 | 4–24 µm |
| C-Ply | 3M (discontinued) | ~16 | 8–16 µm |
| FaradFlex | Oak-Mitsui | ~10–35 | 12–24 µm |

| Supplier | Sanmina | Sanmina | 3M | DuPont |
|----------|---------|---------|-----|--------|
| Trade name | EmCap | BC2000 | C-Ply | HiK |
| Dielectric material | Epoxy Resin/Barium Titanate | FR-4 | Epoxy Resin/Barium Titanate | Polyimide core |
| Thickness µm | 100 | 50 | 25 | 25 |
| Capacitance Range nF/in² | 2.1 | 0.5 | 3.0 | 1.5 |
| Dissipation Factor tan δ 1GHz | 0.06 | 0.021 | 0.1 | 0.01 |
| Dielectric Constant εᵣ 1GHz | 36 | 3.9 | 22 | 11.6 |

*Capacitance material comparison: higher Dk and thinner dielectric = more capacitance per area*

## Advantages

### High-Frequency Performance
Surface-mount capacitors become ineffective above 1 GHz due to parasitic inductance. Embedded capacitors have virtually no lead inductance, providing effective decoupling into the GHz range.

### Reduced Component Count
Each embedded capacitor eliminates a surface-mount part, reducing assembly cost and potential failure points.

### Improved Reliability
No solder joints means no solder fatigue failures. The capacitor is integral to the PCB structure.

### Lower Impedance
The distributed nature of embedded capacitance provides lower ESL (equivalent series inductance) than discrete components.

## Applications

![Cross-section diagram of a board with embedded capacitors showing TEV (Through-board Embedded Via) structure with decoupling and filter capacitors integrated into the PCB layers](/assets/images/technical-library/picture41.webp)

*TEV board structure: embedded capacitors provide local decoupling without consuming surface area*

### Power Integrity
Embedded capacitors work well for mid-frequency decoupling (10 MHz – 1 GHz), complementing bulk capacitors at low frequencies and embedded capacitance layers at high frequencies.

### Filter Networks
RC and LC filters can be implemented with embedded capacitors and [embedded resistors](/technical-library/embedded-resistors/).

### Sensor Applications
Stable, well-characterised capacitors can serve as reference elements in capacitive sensing circuits.

## Limitations

- **Maximum capacitance** is limited by available board area
- **Tolerance** is typically ±20% without trimming
- **Cannot be replaced** after lamination, so design verification is critical
- **Cost premium** for high-Dk materials and additional processing

## When to Use Embedded Capacitors

This technology makes sense when:

- Board space is at a premium and decoupling is required under BGAs
- High-frequency decoupling (>500 MHz) is needed
- Long-term reliability is critical and solder joint failures are a concern
- The design is mature and capacitor values won't change

For distributed power plane capacitance (effective at very high frequencies), see [Embedded Capacitance Layers](/technical-library/embedded-capacitance-layers/).

---

## Industry Status

Embedded capacitor technology using high-Dk materials exists but has limited adoption outside specialized applications. The challenges include:

- **Material availability** - some products (like 3M C-Ply) have been discontinued
- **Supplier qualification** - few PCB manufacturers have production experience
- **Design complexity** - requires careful stackup planning and thermal analysis
- **Cost justification** - discrete capacitors are cheap and well-understood

Military, aerospace, and high-reliability applications use embedded capacitors where the benefits justify the complexity.

---

## Related Articles

- [Embedded Capacitance Layers](/technical-library/embedded-capacitance-layers/) - Power plane configurations with built-in capacitance
- [Embedded Resistors in PCBs](/technical-library/embedded-resistors/) - Resistor embedding using Ohmega-Ply
- [PCB Materials and Laminates Guide](/technical-library/pcb-materials-guide/) - Dielectric material specifications

---

## Questions?

If you're evaluating embedded capacitors for a specific application, [contact us](/contact/). We can discuss the technology and help you understand whether it makes sense for your requirements.

---

<a id="embedded-components-overview"></a>

## Embedded Components in PCBs

> **Archive Note:** This article documents pioneering embedded component technology developed at Shipco by Sten Björsell starting in 2002. While the technology works and several patents were granted, industry-wide manufacturing capability has not matured to the point where embedded active components are readily available from standard PCB suppliers. This content is preserved for educational purposes and historical reference.

## The Problem: Surface-Mount Limits Z-Height and Trace Length

Surface-mount components sit on top of the PCB, consuming vertical space and requiring traces to travel up through vias, across the surface, and back down. In height-constrained products like wearables, implants, and ultra-thin devices, this becomes a hard limit. In high-speed designs, the extra trace length degrades signal integrity.

Embedded component technology solves both problems by placing active devices directly inside the PCB layers, eliminating package height and dramatically shortening signal paths.

## How Embedded Components Work

Active electronic components can be embedded directly into PCB inner layers, eliminating surface-mount assembly for specific components. This technology was developed and refined at Shipco starting in 2002 by engineer Sten Björsell, with several patents granted for the processes involved.

![3D cutaway view of a multilayer PCB with embedded components showing resistors, capacitors, and vias within the layer structure](/assets/images/technical-library/embedded-components-3d-cutaway.webp)

*3D visualization showing embedded passive components (resistors, capacitors) and active devices within PCB inner layers, connected via plated through-holes and micro-vias*

## Key Benefits

### Compact Design
Embedding components inside the PCB layers eliminates the height of surface-mount packages. This enables thinner products and frees board surface area for other components or routing.

### Shorter Signal Paths
With the component inside the board rather than on top, trace lengths to surrounding circuitry are reduced. This improves signal integrity and reduces parasitic inductance.

### Noise Reduction
Embedded active components can be completely shielded by surrounding copper layers, reducing electromagnetic interference both to and from the component.

### Higher Signal Integrity
Fewer via holes and shorter interconnects mean less signal degradation, particularly important for high-speed designs where every millimeter of trace length matters.

## How It Works

The simplest implementation embeds an SMT chip in a multilayer PCB:

1. The component is placed in a cavity or pocket in the inner layers
2. Connections are made via through-hole vias to standard SMT leads, or laser-drilled micro-vias to component pads
3. The connection is formed chemically, then electroplated, with no solder required

This solder-free assembly approach provides reliable connections that can withstand repeated thermal cycling.

**Requirements:** Well-tested and in-circuit fully protected components must be used, since the embedded component cannot be replaced after lamination.

## Production Examples

These microsection images are from production boards manufactured during the development of this technology:

![Flip chip embedded in a PCB connected to micro-vias](/assets/images/technical-library/ad5de2e9-bu1.webp)

*Flip chip embedded in a PCB and connected to micro-vias*

![Flip chip embedded in a PCB and inter-connected to staggered micro-vias](/assets/images/technical-library/4b6984ba-bu2.webp)

*Flip chip with staggered micro-via interconnections*

![Both flip chip and other component embedded in the PCB layers](/assets/images/technical-library/4f25ea66-bu3.webp)

*Multiple embedded components in the same board, flip chip alongside other devices*

![Micro section of a board with an embedded component](/assets/images/technical-library/dedb0e1b-bu8.webp)

*Cross-section showing embedded component within the PCB stackup*

![Trough Hole Connections inter-connecting to an embedded component inside the PCB package](/assets/images/technical-library/79247a96-bu6.webp)

*Through-hole connections to an embedded component*

![Trough Hole Connection with blind Holes Cooling a component embedded directly inside the PCB layers](/assets/images/technical-library/fe90d310-bu7.webp)

*Thermal management: through-holes provide heat dissipation path for embedded component*

## When Embedded Components Make Sense

This technology addresses real problems when:

- **Height is constrained** - the product requires minimal Z-height
- **Signal integrity is critical** - high-speed designs benefit from shorter traces
- **Shielding is required** - sensitive circuits need complete electromagnetic isolation
- **Reliability is paramount** - solder-free connections eliminate a common failure mode

---

## Industry Status

Despite the technical viability demonstrated in the early 2000s, embedded active component technology has not achieved widespread adoption. The reasons include:

- **Limited supplier base** - very few PCB manufacturers have qualified processes
- **Design tool support** - standard EDA tools don't natively support embedded component design
- **Component availability** - bare die and known-good-die sourcing remains challenging
- **Risk aversion** - the inability to rework embedded components concerns many designers

Embedded passive components (resistors, capacitors) have seen more adoption, particularly in military and aerospace applications where the benefits justify the complexity.

---

## Related Articles

- [Embedded Resistors in PCBs](/technical-library/embedded-resistors/) - Passive resistor embedding with Ohmega-Ply
- [Embedded Capacitors in PCBs](/technical-library/embedded-capacitors/) - Capacitor embedding techniques
- [Embedded Capacitance Layers](/technical-library/embedded-capacitance-layers/) - Power plane configurations
- [Micro-Via Advantages in PCBs](/technical-library/micro-via-advantages/) - HDI routing for embedded designs

---

## Interested in Pushing Boundaries?

If you're working on a project where embedded component technology could provide significant advantages and you're willing to work through the manufacturing challenges, [contact us](/contact/) to discuss what might be possible. We can share what we learned during development and help evaluate whether this approach makes sense for your specific application.

---

<a id="embedded-resistors"></a>

## Embedded Resistors in PCBs

> **Archive Note:** Embedded resistor technology is technically mature and used in production, particularly in military, aerospace, and high-reliability applications. However, the number of PCB manufacturers offering this capability remains limited, and finding qualified suppliers requires lead time. This article explains the technology for educational purposes.

## The Problem: Termination Resistors Everywhere

High-speed designs require termination resistors at the end of every controlled impedance trace. In a dense design with hundreds of nets, that means hundreds of small resistors, each consuming board space, adding assembly cost, and creating potential failure points.

Embedded resistors integrate these passives directly into the PCB, eliminating surface-mount components without sacrificing functionality.

## How Embedded Resistors Work

There are two main approaches:

### Resistive Foil (Ohmega-Ply)

A thin nickel-phosphorus alloy layer is bonded to copper foil before lamination. During PCB fabrication, the copper is etched to define the resistor geometry, leaving the resistive layer to form the actual resistance.

The resistance depends on:
- **Sheet resistivity** - material property, measured in Ω/square
- **Geometry** - length and width of the resistive element

**Formula**: R = (L/W) × Rₛ

Where:
- **R** = Resistance (ohms)
- **L** = Length of resistor element
- **W** = Width of resistor element
- **Rₛ** = Sheet resistivity (Ω/square)

### Carbon Ink (Screen Printed)

Carbon-loaded polymer ink is screen printed onto inner or outer layers. This is an older technology, lower precision, but also lower cost.

## Ohmega-Ply Specifications

Ohmega-Ply is available in several sheet resistivities:

| Sheet Resistivity | Typical Applications |
|-------------------|---------------------|
| 25 Ω/square | Low-value resistors, bus termination |
| 50 Ω/square | General purpose |
| 100 Ω/square | Most common, good range of values |
| 250 Ω/square | Higher value resistors |

More information: [Ohmega Technologies](http://www.ohmega.com/technology/)

## Calculation Example

**Given:**
- Sheet resistivity: 100 Ω/square
- Required resistance: 500 Ω

**Calculation:**
- Squares needed: 500 ÷ 100 = 5 squares
- If trace width is 0.4 mm (16 mil), length = 5 × 0.4 mm = 2.0 mm (80 mil)

**Verification**: R = (2.0/0.4) × 100 = 500 Ω ✓

![Top and bottom views of a PCB with embedded Ohmega-Ply resistors, showing dense routing with resistor elements integrated into inner layers](/assets/images/technical-library/picture40.webp)

*PCB with embedded resistors: complex routing with Ohmega-Ply resistive elements on inner layers*

## Carbon Ink Option

For lower-precision applications, carbon paste offers a simpler alternative:

![Diagram of carbon paste resistor showing rectangular geometry with copper pads at each end](/assets/images/technical-library/picture37.webp)

*Carbon paste resistor geometry: resistance determined by length-to-width ratio*

**Carbon paste specifications:**
- Resistance range: 20 Ω – 150 kΩ
- Tolerance: ±25% (>100 Ω), ±40% (<100 Ω)
- Other values possible depending on paste availability

Carbon ink is screen printed and cured. It's commonly used for:
- Membrane switches
- Keypad contacts
- Low-precision termination
- Cost-sensitive applications

## Tolerances

| Method | Standard Tolerance | With Laser Trimming |
|--------|-------------------|---------------------|
| Ohmega-Ply | ±10–15% | ±1% |
| Carbon ink | ±20–30% | ±5–10% |

Laser trimming measures each resistor and cuts a precise trim path to dial in the exact value. This adds cost but enables tight tolerances regardless of initial material variation.

## Design Considerations

### Keep It Simple
Embedded resistors work best for:
- Fixed values that won't change
- Moderate tolerance requirements
- High quantities where assembly savings matter

### Temperature Coefficient
Embedded resistors have temperature coefficients (TCR) that affect precision applications. Ohmega-Ply TCR is typically ±100 ppm/°C, acceptable for termination but not precision measurement.

### Power Handling
Maximum power depends on thermal dissipation. Rule of thumb: 50–100 mW per resistor for buried elements, more for surface-exposed resistors with good thermal path.

### Layer Placement
Embedded resistors are typically placed on inner layers close to the surface (layer 2 or n-1). This simplifies the stackup while keeping resistors accessible for trimming if needed.

## When to Use Embedded Resistors

This technology makes sense when:

- You have many resistors of the same or similar values (termination networks)
- Board space is constrained
- High reliability is required (no solder joints to fail)
- The design is stable and resistor values won't change
- Volume justifies the NRE for resistive foil material

---

## Industry Status

Embedded resistor technology using Ohmega-Ply or similar materials is more established than embedded active components, but supplier availability remains limited. Military and aerospace applications use embedded resistors in production, but commercial adoption has been slow due to:

- Higher upfront costs compared to discrete SMT resistors
- Limited PCB supplier base with qualified processes
- Design inflexibility once values are committed to artwork

---

## Related Articles

- [Embedded Capacitors in PCBs](/technical-library/embedded-capacitors/) - Forming capacitors within PCB layers
- [Embedded Components Overview](/technical-library/embedded-components-overview/) - Active component embedding technology
- [PCB Materials and Laminates Guide](/technical-library/pcb-materials-guide/) - Material selection for embedded designs

---

## Questions?

If you're evaluating embedded resistors for a specific application, [contact us](/contact/). We can discuss the technology and help you understand whether it makes sense for your requirements.

---

<a id="embedded-transformers"></a>

## Planar Transformers in PCBs

## The Problem: Wire-Wound Transformers Limit Power Density

Traditional wire-wound transformers are bulky, expensive to manufacture, and difficult to integrate with modern surface-mount assembly. In power supplies where size matters—think portable devices, distributed power, and space-constrained applications—conventional magnetics become the limiting factor.

Planar transformers solve this by etching the windings directly into PCB layers, creating flat, repeatable, easily assembled magnetic components.

## How Planar Transformers Work

Instead of wire wound around a bobbin, planar transformers use spiral traces on PCB layers as windings. A ferrite core (typically an E-core or ER-core) clamps around the PCB, completing the magnetic circuit.

**Key differences from wire-wound:**
- Windings are photolithographically defined—perfectly repeatable
- Very low profile (determined by ferrite core height)
- Excellent thermal characteristics (copper spread across PCB area)
- Interleaving of primary and secondary is easy (just stack layers)
- 100% compatible with surface-mount assembly

## Advantages

### High Efficiency
Planar transformers routinely achieve 94% efficiency or higher. The flat, wide conductors have lower AC resistance at high frequencies than round wire.

### Low Profile
With the right core selection, total height can be under 10 mm—often 5–6 mm for lower power designs.

### Excellent Repeatability
Every transformer is identical because the windings are defined by PCB artwork. No hand-winding variation.

### Low Noise
The tight coupling between layers and controlled geometry results in lower leakage inductance and reduced EMI compared to wire-wound designs.

### Integrated Design
The transformer can be part of the main PCB (windings on inner layers) or a separate module that mounts like any SMT component.

## Typical Specifications

| Parameter | Typical Range |
|-----------|---------------|
| Power | 5 W – 500 W |
| Efficiency | 90–96% |
| Operating frequency | 50 kHz – 2 MHz |
| Isolation voltage | 500 V – 4 kV (depends on stackup) |
| Profile height | 4–15 mm |

![Photograph of a planar DC/DC converter module rated for 150 W output power with 94% efficiency, showing the flat profile and surface-mount construction](/assets/images/technical-library/picture36.webp)

*Planar DC/DC converter: 150 W, 94% efficiency, 100% surface mounted*

## Design Approaches

### Integrated Windings
The transformer windings are etched on inner layers of the main PCB. The ferrite core mounts on top. This minimises parts count but constrains the main PCB stackup.

### Separate Module
A dedicated transformer PCB with [castellated holes](/technical-library/castellated-holes-edge-plating/) or standard SMT pads. The module is assembled separately, tested, then soldered to the main board like any component.

**Advantages of separate module:**
- Transformer can be fully tested before assembly
- Main PCB stackup is not constrained
- Ferrite assembly happens offline
- Easier to second-source or redesign independently

## Layer Count Considerations

The number of PCB layers depends on:
- **Turns ratio** – more turns = more layers
- **Current capacity** – parallel layers for high current
- **Isolation requirements** – dedicated isolation layers may be needed

A simple 1:1 transformer might need only 4 layers. A complex multi-output design could require 12 or more.

## When to Consider Planar Transformers

This technology makes sense when:

- **Height is constrained** – planar designs are significantly flatter than wire-wound
- **Repeatability matters** – production volumes benefit from photolithographic consistency
- **High frequency operation** – planar windings have lower AC resistance
- **EMI is critical** – controlled geometry reduces leakage inductance
- **Surface-mount assembly is required** – no hand-winding or through-hole insertion

## Suppliers

You can design planar transformers in-house or source from specialists:

- Payton Planar (US)
- Standex-Meder Electronics (EU/US)
- Coilcraft (standard modules)
- Custom designs from any PCB-capable transformer manufacturer

---

## Related Articles

- [How Multilayer PCBs Are Made](/technical-library/how-to-build-pcbs/) – Fabrication process for multilayer designs
- [Castellated Holes and Edge Plating](/technical-library/castellated-holes-edge-plating/) – Mounting options for PCB modules
- [PCB Materials and Laminates Guide](/technical-library/pcb-materials-guide/) – Material selection for power applications

---

**Interested in planar transformer PCBs?** [Contact us](/contact/) to discuss your power conversion requirements.

---

<a id="flex-pcb-capability-limits"></a>

## Flex PCB Capability Limits

Flexible PCBs require different design rules than rigid boards. The polyimide substrate, adhesive layers, and coverlay all affect what's achievable. Here's what we can manufacture.

## Layer Count and Thickness

| Parameter | Standard | Advanced |
|-----------|----------|----------|
| **Layer count** | 1–4 layers | 5–8 layers |
| **Board thickness** (without stiffener) | 0.05–0.5mm | 0.5–0.8mm |
| **Thickness tolerance** (single layer) | ±0.05mm | ±0.03mm |
| **Thickness tolerance** (multilayer <0.3mm) | ±0.05mm | ±0.03mm |
| **Thickness tolerance** (multilayer 0.3–0.8mm) | ±0.1mm | ±10% |

## Bend Radius Requirements

The minimum bend radius depends on your layer count and whether the flex will bend repeatedly:

| Configuration | Minimum Bend Radius |
|---------------|---------------------|
| **Single layer** (static bend) | 3–6× board thickness |
| **Double layer** (static bend) | 6–10× board thickness |
| **Multilayer** (static bend) | 10–15× board thickness |
| **Dynamic bend** (repeated flexing) | 20–40× board thickness |

*Dynamic bend applications require single-layer construction for reliability.*

## Line Width and Spacing

Achievable trace geometries depend on copper weight:

| Copper Weight | Standard (width/space) | Advanced (width/space) |
|---------------|------------------------|------------------------|
| **12–18μm (⅓–½oz)** | 3.0/3.2 mil | 2.8/2.7 mil |
| **35μm (1oz)** | 4.0/4.0 mil | 3.5/3.5 mil |
| **70μm (2oz)** | 6.0/6.5 mil | 5.0/6.0 mil |
| **105μm (3oz)** | 10/13 mil | 9.5/12.5 mil |

*Note: Loop lines (traces that return to the same point) require approximately double the width/space.*

## Materials

### Base Materials (FCCL)

**Adhesive-based:**
- Shengyi SF305: PI 0.5–2 mil, Cu ⅓–1oz
- Panasonic R-F775: PI 1–3 mil, Cu ½–1oz
- Taiflex MHK: PI 1–2 mil, Cu ⅓–1oz

**Adhesiveless:**
- DuPont Pyralux AP: PI 1–3 mil (standard), 4 mil (advanced), Cu ½–2oz
- Taiflex MHK: PI 1–2 mil, Cu ⅓–1oz

### Coverlay
- Shengyi SF305C
- Taiflex FHK

### Stiffeners
- **PI stiffener:** 3–9 mil thickness
- **FR4 stiffener:** Available with ±0.1mm tolerance

## Drilling and Holes

| Parameter | Standard | Advanced |
|-----------|----------|----------|
| **Minimum mechanical drill** | 6 mil (0.15mm) | 4 mil (0.1mm) |
| **Via-to-conductor clearance** (<4 layer) | 6 mil | 5 mil |
| **Via-to-conductor clearance** (4–6 layer) | 8 mil | 7 mil |
| **Via-to-conductor clearance** (7–8 layer) | 12 mil | 10 mil |

## Surface Finishes

Available finishes for flex PCBs:

- **HASL** – Hot air solder leveling
- **ENIG** – Electroless nickel immersion gold (Ni: 3–6μm, Au: 0.05–0.1μm)
- **ENEPIG** – Electroless nickel electroless palladium immersion gold
- **Electrolytic gold** – Soft or hard gold options
- **Immersion silver** – 0.2–0.4μm thickness
- **OSP** – Organic solderability preservative
- **Immersion tin** – Advanced capability only

Mixed finishes (ENIG+OSP, ENIG+gold finger) are also available.

## Board Size

| Parameter | Standard | Advanced |
|-----------|----------|----------|
| **Minimum size** (without bridge) | 5×10mm | 4×8mm |
| **Minimum size** (with bridge) | 10×10mm | 8×8mm |
| **Maximum size** | 9×14 inch | 9×23 inch |

## Impedance Control

| Type | Standard Tolerance | Advanced Tolerance |
|------|-------------------|-------------------|
| **Single-ended ≤50Ω** | ±5Ω | ±3Ω |
| **Single-ended >50Ω** | ±10% | ±8% |
| **Differential ≤50Ω** | ±5Ω | ±4Ω |
| **Differential >50Ω** | ±10% | ±8% |

## Solder Mask

- **Colors:** Green standard, others available
- **Minimum solder dam:** 4 mil (green), 8 mil on large copper areas
- **Minimum clearance:** 3 mil (2.5 mil for specific areas)
- **Coverlay bridge minimum:** 8 mil

---

## Related Articles

- [Multilayer PCB Capabilities](/technical-library/pcb-capability-limits/) – Rigid PCB specifications for comparison
- [PCB Materials and Laminates Guide](/technical-library/pcb-materials-guide/) – Material properties and selection
- [PCB Designer's Tips](/technical-library/pcb-designers-help/) – Design guidelines for manufacturability

---

**Need help with a flex PCB design?** [Request a quote](/quote/) – our engineers can review your design for manufacturability and recommend the best construction.

---

<a id="how-to-build-pcbs"></a>

## How Multilayer PCBs Are Made: Step-by-Step Fabrication Guide

Understanding PCB fabrication helps you design boards that are easier and cheaper to manufacture. A typical multilayer PCB requires around 50 process steps involving specialized equipment, precise chemistry, and careful quality control at each stage.

This guide walks through the complete fabrication process in two parts: inner layer preparation and final board production.

![PCB fabrication equipment overview](/assets/images/technical-library/pcb-fabrication/cam-equipment-overview.webp)

*CAM station outputs data to plotters, drills, AOI, routers, and test equipment*

---

## Part 1: Inner Layer Preparation

### CAM Engineering

Every PCB starts in the CAM (Computer-Aided Manufacturing) department, where your design files are prepared for production.

**Input data formats accepted:**
- Gerber (RS-274X)
- ODB++
- DPF, DXF, HPGL
- IPC-356 netlist

**CAM preparation steps:**

1. **Data input** — Import design, drill, drawing, netlist, and specification files
2. **Layer definition** — Assign outer layers, inner layers, solder mask, legend, and drill files
3. **Design rules check (DRC)** — Verify against customer specs, IPC standards, and factory capabilities
4. **Panelization** — Step PCB onto production panel with frame, tooling holes, and test coupons
5. **Compensation** — Apply etch compensation, scaling factors, and final checks
6. **Output** — Generate data for plotters, LDI, drill, plating, AOI, routing, and electrical test

### Material Selection

![Laminate material storage](/assets/images/technical-library/pcb-fabrication/laminate-material-storage.webp)

*Laminate inventory: different materials, thicknesses, and copper weights ready for production*

Inner layer cores are selected based on your stackup requirements:

| Parameter | Common Options |
|-----------|----------------|
| **Material** | FR-4, High-Tg FR-4, Rogers RO4350, Teflon, Polyimide |
| **Dielectric thickness** | 0.1, 0.2, 0.3, 0.4mm and others |
| **Copper weight** | 18, 35, 70, 105μm (½oz, 1oz, 2oz, 3oz) |

### Surface Pretreatment

![Pretreatment line](/assets/images/technical-library/pcb-fabrication/pretreatment-line.webp)

*Horizontal conveyorized pretreatment line for cleaning copper surfaces*

Before imaging, copper surfaces must be:
- **Cleaned** — Remove oxidation, oils, and contaminants
- **Micro-roughened** — Create surface texture for dry film adhesion

This is done mechanically (pumice scrubbing) or chemically. The goal is a clean, oxide-free surface with consistent micro-roughness.

### Dry Film Lamination

![Dry film laminator](/assets/images/technical-library/pcb-fabrication/dry-film-laminator.webp)

*Hot roll laminator applying photosensitive dry film to copper surface*

Photosensitive dry film resist is applied using heat and pressure. The film protects areas that will remain copper and exposes areas to be etched away.

### Pattern Imaging

There are two methods for transferring the circuit pattern onto the dry film:

**Contact Printing (Phototool)**

![Film plotter](/assets/images/technical-library/pcb-fabrication/film-plotter.webp)

*Film plotter producing silver halide phototools*

Silver films are plotted and used as contact copies. UV light passes through clear areas to expose the dry film beneath.

**Laser Direct Imaging (LDI)**

![LDI machine](/assets/images/technical-library/pcb-fabrication/ldi-machine.webp)

*Laser Direct Imaging system for filmless exposure*

LDI uses CAM data directly—no phototools required. Benefits include:
- Higher accuracy (no film distortion)
- Automatic scaling to match pre-drilled registration holes
- Faster setup for prototype and quick-turn work

### Develop, Etch, Strip (DES)

![DES line](/assets/images/technical-library/pcb-fabrication/des-line.webp)

*Develop-etch-strip processing line*

After exposure, panels go through the DES line:

1. **Develop** — Mild sodium carbonate solution (~1%) removes unexposed dry film
2. **Etch** — Acidic or alkaline etchant removes exposed copper, leaving the circuit pattern
3. **Strip** — Remaining dry film is chemically removed, revealing finished copper traces

The cross-sections below show the inner layer at each stage:

![Inner layer with developed dry film](/assets/images/technical-library/pcb-fabrication/inner-layer-developed-dry-film.webp)

*Inner layer after develop: dry film (blue) protects circuit pattern, copper exposed where it will be etched*

![Etched inner layer](/assets/images/technical-library/pcb-fabrication/inner-layer-etched.webp)

*Inner layer after etch and strip: copper traces remain where protected by dry film*

### Automated Optical Inspection (AOI)

Every inner layer is inspected by AOI before lamination. The system:
- Compares the actual panel against CAM data
- Checks trace widths and spacing against design rules
- Identifies opens, shorts, and contamination
- **Eliminates 100% of defective inner layers** before they're buried in the stackup

This is critical—inner layer defects cannot be repaired after lamination.

### Layer Registration

![Layer registration diagram](/assets/images/technical-library/pcb-fabrication/layer-registration-diagram.webp)

*Registration targets on inner layers must align precisely—misalignment causes drill breakout*

All inner layers must align precisely when stacked. The post-etch punch:
- Uses cameras to locate targets or drilled holes on each layer
- Automatically aligns and punches registration holes
- Compensates for any material movement during processing

### Layup and Lamination

![Inner layer panel artwork](/assets/images/technical-library/pcb-fabrication/inner-layer-panel-artwork.webp)

*Panelized inner layer ready for layup—multiple PCBs stepped on production panel*

Inner layers, prepreg, and copper foil are stacked according to the stackup design:

1. Layers are pinned to steel caul plates for alignment
2. The stack is placed in a vacuum press
3. Heat and pressure cure the prepreg resin, bonding all layers

Different materials require specific press cycles—temperature ramps, pressure profiles, and cure times are all programmed for each material system.

### X-Ray Registration

![Panel with registration targets](/assets/images/technical-library/pcb-fabrication/panel-with-registration-targets.webp)

*Inner layer targets (circled) visible through laminate—X-ray system locates these for drilling*

After pressing, material movement must be compensated. The X-ray punch:
- Sees copper targets buried inside the panel
- Calculates optimal position for new registration holes
- Ensures subsequent drilling aligns with inner layer features

---

## Part 2: Final Board Production

For double-sided boards, production starts here. For multilayers, this continues from the laminated panel.

### Drilling

Most holes are mechanically drilled at this stage:

- **Standard via sizes**: 0.3mm and larger
- **Small holes** (≤0.3mm) reduce drill stack height and increase cost
- **Thick panels** also limit stack height

![Multilayer drilled cross-section](/assets/images/technical-library/pcb-fabrication/multilayer-drilled-cross-section.webp)

*Cross-section after mechanical drilling: through-hole connects all layers, but hole walls are not yet conductive*

### Laser Drilling (for HDI)

![ESI Laser via drill](/assets/images/technical-library/pcb-fabrication/laser-via-drill-esi.webp)

*ESI 5200 UV laser drilling system for micro-vias*

Micro-vias (typically 100-150μm) require laser drilling. See our [micro-via advantages guide](/technical-library/micro-via-advantages/) for when HDI makes sense.

### Electroless Copper Deposition

![Plating line with copper panels](/assets/images/technical-library/pcb-fabrication/plating-line-copper-panels.webp)

*Vertical plating line—panels move through chemical baths on flight bars*

This critical process deposits a thin conductive copper layer on hole walls, enabling subsequent electroplating. It involves multiple chemical baths:

- Cleaner/conditioner
- Micro-etch
- Catalyst (palladium-based)
- Electroless copper

The quality of this step determines plated through-hole reliability.

![Electroless copper cross-section](/assets/images/technical-library/pcb-fabrication/electroless-copper-cross-section.webp)

*After electroless copper: thin conductive layer now coats hole walls*

### Outer Layer Imaging

The outer layer process mirrors inner layer imaging:

![Outer layer lamination](/assets/images/technical-library/pcb-fabrication/outer-layer-lamination.webp)

*Dry film lamination for outer layers*

1. **Laminate dry film**
2. **Expose pattern** — Contact print or LDI
3. **Develop** — Remove unexposed resist

### Pattern Plating

Unlike inner layers (which are etched from solid copper), outer layers are pattern plated:

1. **Electroplate copper** — Build up copper in exposed areas (traces and pads)
2. **Electroplate tin** — Etch resist to protect copper during etching
3. **Strip dry film** — Remove photoresist
4. **Etch copper** — Remove base copper between traces
5. **Strip tin** — Remove tin etch resist

![Outer layer plated cross-section](/assets/images/technical-library/pcb-fabrication/outer-layer-plated-cross-section.webp)

*After pattern plating: copper built up on traces and in holes, dry film (blue) still in place*

### Outer Layer AOI

![Outer layer AOI](/assets/images/technical-library/pcb-fabrication/aoi-outer-layer.webp)

*AOI inspection of outer layer patterns*

Outer layers are inspected by AOI before solder mask application.

### Solder Mask Application

![Solder mask coating](/assets/images/technical-library/pcb-fabrication/solder-mask-curtain-coater.webp)

*Curtain coater applying liquid photoimageable solder mask*

Solder mask protects copper from oxidation and prevents solder bridging during assembly. Application methods:

| Method | Description |
|--------|-------------|
| **Curtain coating** | Liquid mask flows over panel in a curtain |
| **Screen printing** | Mask squeegeed through mesh screen |
| **Electrostatic spray** | Charged particles deposited evenly |

![Solder mask coated cross-section](/assets/images/technical-library/pcb-fabrication/solder-mask-coated-cross-section.webp)

*After solder mask coating: green mask covers board surface before imaging*

After coating, the mask is exposed and developed like dry film, leaving openings for pads and vias.

![Solder mask exposure cross-section](/assets/images/technical-library/pcb-fabrication/solder-mask-exposure-cross-section.webp)

*During solder mask exposure: film masks (black bars) block UV over pad areas to keep them open*

### Surface Finish

The exposed copper pads need protection from oxidation. Common finishes:

**ENIG (Electroless Nickel / Immersion Gold)**

![ENIG line](/assets/images/technical-library/pcb-fabrication/enig-line.webp)

*Chemical plating line for ENIG surface finish*

- Flat surface for fine-pitch BGAs
- Good shelf life
- Higher cost than HASL

**Other finishes:**
- **HASL** — Hot air solder leveling, traditional finish, excellent solderability
- **OSP** — Organic coating over copper, lowest cost, limited shelf life

![Surface finish cross-section](/assets/images/technical-library/pcb-fabrication/surface-finish-cross-section.webp)

*Finished board cross-section: solder mask (green) with surface finish on exposed pads*

### Electrical Test

Every board is electrically tested for opens and shorts.

**Flying Probe Testing**

![Flying probe tester](/assets/images/technical-library/pcb-fabrication/flying-probe-tester.webp)

*EMMA flying probe test system—probes move to test each net*

- Moving probes test directly from CAM data
- No fixture required
- Ideal for prototypes and small batches

**Fixture Testing**

![Probe fixture diagram](/assets/images/technical-library/pcb-fabrication/probe-fixture-diagram.webp)

*Fixture test concept: spring-loaded pins contact all test points simultaneously*

- Dedicated fixture with spring-loaded pins
- Very fast for high-volume production
- Fixture fabrication adds time and cost

### Routing and Scoring

Boards are separated from the production panel by:

- **Routing** — CNC router cuts board outline (standard: 2.4mm cutter, minimum: 0.8mm)
- **Scoring** — V-groove allows panels to snap apart after assembly
- **Combination** — Routed outlines with breakaway tabs

![V-scoring diagram](/assets/images/technical-library/pcb-fabrication/v-scoring-diagram.webp)

*V-score specifications: 30° blade angle, minimum 0.4mm from score to copper, 0.2-0.35mm remaining material*

### Final Inspection

![Visual inspection](/assets/images/technical-library/pcb-fabrication/visual-inspection-operator.webp)

*Visual inspection with magnification lamp*

Final QC checks:
- Dimensional accuracy
- Surface finish quality
- Bow and twist (flatness)
- Cosmetic defects
- Compliance with specifications

![Finished PCB panel](/assets/images/technical-library/pcb-fabrication/finished-pcb-panel.webp)

*Finished PCB panel ready for shipment*

---

## Why This Matters for Your Design

Understanding fabrication helps you:

1. **Avoid costly design changes** — Know what's easy vs. difficult to manufacture
2. **Specify appropriately** — Don't over-specify tolerances you don't need
3. **Communicate effectively** — Use correct terminology with your manufacturer
4. **Troubleshoot issues** — Understand root causes when problems occur

For stackup guidance, see our [PCB build illustrations](/pcb-build-illustrations/) showing common multilayer constructions.

---

**Questions about your design?** Our engineers review manufacturability at no charge. [Get in touch](/contact/).

---

<a id="micro-via-advantages"></a>

## Micro-Via Advantages in PCBs

Micro-vias are laser-drilled holes (typically 100–150μm diameter) that connect adjacent layers in HDI PCBs. Unlike mechanically drilled through-holes, micro-vias enable higher density routing and improved electrical performance. Here's why designers choose micro-via technology.

## Key Benefits

### Shorter Signal Paths
Micro-vias connect only adjacent layers, eliminating the long vertical stubs created by through-hole vias. This results in:
- **Shorter trace lengths** – signals travel less distance
- **Fewer signal layers needed** – more efficient routing in less space
- **Better signal integrity** – reduced inductance and capacitance

### Improved High-Frequency Performance
The shorter signal paths directly benefit RF and high-speed designs:
- **Enhanced RF capability** – less parasitic inductance
- **Improved EMC characteristics** – reduced radiation and coupling
- **Cleaner impedance control** – fewer discontinuities in transmission lines

### Higher Component Density
Micro-vias unlock routing options that aren't possible with through-holes:
- **More room for components** – via-in-pad allows placement directly under BGAs
- **Single-sided assembly becomes viable** – avoiding the cost of double-sided placement
- **Smaller PCB footprint** – same functionality in less board area

For maximum component density, consider the [R7011 build](/pcb-build-illustrations/#r7011) which combines buried vias with micro-vias on both surfaces.

### Better Reliability
Contrary to early concerns, micro-vias have proven more reliable than through-holes:
- **Lower thermal stress** – smaller copper volume expands less during reflow
- **No barrel cracking** – the failure mode that affects long through-holes
- **Proven in automotive and aerospace** – extensively tested per IPC standards

### Additional Advantages
- **Embedded passives possible** – resistors can be integrated on layers 2 and n-1
- **Fewer drilled holes** – reduces drilling time and tool wear
- **Environmentally friendly** – less material waste than mechanical drilling

## When to Use Micro-Vias

Micro-via HDI technology makes sense when:
- BGA pitch is 0.8mm or less and fanout requires via-in-pad
- Signal integrity requirements demand controlled impedance with minimal stubs
- Board size is constrained and through-hole routing won't fit
- High-frequency operation (>1GHz) requires minimal parasitic effects

For simpler designs with larger BGAs (1.0mm+ pitch), standard [multilayer builds with blind vias](/pcb-build-illustrations/#multilayer) may be more cost-effective.

## Micro-Via Examples

![BGA breakout pattern showing micro-via routing](/assets/images/technical-library/picture35.webp)

*BGA fanout example: 64 contacts, 0.8mm pitch, 0.3mm pad, 0.15mm trace/space, 0.3mm vias, 0.1mm micro-vias*

![Laser-drilled micro-via cross-section](/assets/images/technical-library/microvia.webp)

*UV laser-drilled micro-via in RCC (resin-coated copper) foil: 0.1mm diameter, stepped 0.2mm to 0.1mm*

## Learn More

- [PCB Build Illustrations](/pcb-build-illustrations/#hdi) – see micro-via stackups R7009–R7020
- [Multilayer PCB Stackups](/pcb-build-illustrations/#multilayer) – compare HDI vs. standard constructions
- [Reliability Testing for Microvias in Printed Wire Boards](https://magazines007.com/pdf/EIPC_Conference_Paper-1.pdf) (PDF) – EIPC conference paper on micro-via reliability

---

**Need help with an HDI design?** Our engineers can review your stackup and recommend the most practical micro-via configuration. [Get in touch](/contact/).

---

<a id="pcb-capability-limits"></a>

## Multilayer PCB Capabilities

## Understanding What's Manufacturable

Before finalising your PCB design, you need to know: can it actually be built? Manufacturing capabilities vary by factory and technology. This reference covers our standard and advanced capabilities—use it to ensure your design is manufacturable and to understand what pushes into premium territory.

## Evidence From Supplied Boards

Our production history contains more than 8,000 distinct supplied bare-PCB designs. Within the available manufacturing specifications, we have supplied:

- More than 1,800 high-Tg projects
- More than 500 controlled-impedance projects
- More than 300 projects with blind and/or buried vias
- More than 200 projects with resin-filled via-in-pad
- Heavy-copper builds through 5 oz

These rounded figures are delivered-job observations, not theoretical factory limits. The standard portfolio table below remains 1-40 layers. Material availability and advanced limits vary by construction, so we confirm the complete stackup before production.

## Outer and Inner Layer Tolerance Limits

![Cross-section diagram showing inner layer clearance requirements around plated holes, with dimensions for trace-to-hole spacing](/assets/images/technical-library/picture321.webp)

*Inner layer clearance: minimum spacing from trace edge to hole wall depends on layer count and hole size*

**Key dimensions:**
- **A**: For material <0.8 mm, minimum via is 0.2 mm; for thicker material, minimum via is 0.3 mm
- **B**: Outer layer pads can be landless (no annular ring) in some configurations

### Design Rules Check: Inner Layer Clearance Can Be Ambiguous

For inner layers, the design rules check "clearance trace to plated hole edge" is not always interpreted consistently. See the illustration above - the double arrow marks the correct clearance distance of 200 µm. This must be measured from the drill hole edge, not the finished (plated) hole edge.

CAD systems typically work with finished hole sizes. With a 150 µm (6 mil) oversize drill to allow for plating (3 mil each side), a DRC setting of 200 µm will actually pass designs with only 125 µm clearance - which is not safe to manufacture. The setting must be increased by 75 µm to 275 µm total.

**Check this before using a new CAD system.** Incorrect interpretation of this rule causes significant rework or unusable layouts.

---

## Board Specifications

| Parameter | Capability |
|-----------|------------|
| Layer count | 1-40 layers |
| Board thickness | 0.13-7.0 mm |
| Maximum board size | 23 × 35 inch (584 × 889 mm) |
| Minimum core thickness | 0.05 mm (standard), 0.13 mm (blind/buried via) |
| Maximum inner layer copper | 10 oz |
| Minimum warpage | 0.10% |

---

## Materials

### Standard FR-4

| Material | Tg | Notes |
|----------|-----|-------|
| S1144 | 130°C min | Standard for 2-layer boards |
| S1141 150 | 145°C min | Minimum Tg for lead-free multilayer |
| S1155 | 130°C min | Halogen-free |
| S1165 | 170°C min | Halogen-free, excellent pad bond strength for repeat soldering |

### High-Tg FR-4

FR408, IT180A, PLC-370HR, N4000-13, N4000-13SI

### RF/Microwave Materials

**Hydrocarbon ceramic:** Rogers 4350, Rogers 4003, Arlon 25FR, Arlon 25N

**PTFE laminates:** Rogers, Taconic, Arlon, Nelco series

**PTFE bonding films:** RO3001 (1.5 mil), HTI.5 (1.5 mil), Cuclad 6700 (1.5 mil)

**PTFE prepregs:** Gore Speed Board C (1.5, 2.0, 2.2, 3.4 mil), Taconic TPG-30/32/35 (4.5, 5.0 mil)

### HDI Materials

| Material Type | Specification |
|---------------|---------------|
| RCC (Resin Coated Copper) | 12 µm copper, 65 or 100 µm resin |
| LDPP (Laser Drill Prepreg) | IT-180A 1037 (2.0 mil), IT-180A 1086 (3.0 mil) |

---

## Trace and Space

### Inner Layer (Width/Space)

| Copper Weight | Min Width/Space |
|---------------|-----------------|
| 1/3-1/2 oz | 3/3 mil (75/75 µm) |
| 1 oz | 3/4 mil (75/100 µm) |
| 2 oz | 5/5 mil (125/125 µm) |
| 3 oz | 6/7 mil (150/175 µm) |
| 4 oz | 7/11 mil (175/275 µm) |
| 5 oz | 10/16 mil (250/400 µm) |

### Outer Layer (Width/Space)

| Copper Weight | Min Width/Space |
|---------------|-----------------|
| 1/3 oz (12 µm) | 3/3 mil (75/75 µm) |
| 1/2 oz | 3.5/3.5 mil (90/90 µm) |
| 1 oz | 4.5/5 mil (115/125 µm) |
| 2 oz | 6/8 mil (150/200 µm) |
| 3 oz | 8/14 mil (200/350 µm) |
| 4 oz | 10/16 mil (250/400 µm) |
| 5 oz | 12/20 mil (300/500 µm) |

### Line Width Tolerance

| Width | Tolerance |
|-------|-----------|
| < 10 mil | ±1.0 mil |
| ≥ 10 mil | ±1.5 mil |

---

## Holes and Vias

### Mechanical Drilling

| Parameter | Capability |
|-----------|------------|
| Finished hole size range | 0.10-6.5 mm |
| Min hole for PTFE material | 0.25 mm |
| Min blind/buried via | 0.30 mm |
| Min connection hole | 0.35 mm |
| Resin plugging range | 0.10-0.40 mm |
| Hole position tolerance | ±3 mil |
| PTH size tolerance | ±3 mil |
| Press-fit PTH tolerance | ±2 mil |
| NPTH size tolerance | ±2 mil (+0/-2 or +2/-0) |

### Laser Drilling (HDI)

| Parameter | Capability |
|-----------|------------|
| Min laser via (depth < 65 µm) | 0.10 mm |
| Min laser via (depth < 100 µm) | 0.13 mm |
| Blind via for resin fill | 0.075-0.15 mm |
| Blind via for copper fill | 0.075-0.127 mm |
| Min pad size (depth < 65 µm) | 10 mil (0.25 mm) |
| Min pad size (depth < 100 µm) | 11 mil (0.28 mm) |

### Aspect Ratio

| Drill Diameter | Max Board Thickness | Aspect Ratio |
|----------------|---------------------|--------------|
| 0.10 mm | 0.6 mm | 6:1 |
| 0.15 mm | 1.2 mm | 8:1 |
| > 0.20 mm | - | 16:1 max |

### Resin Plug Hole Size by Board Thickness

| Board Thickness | Max Hole Size |
|-----------------|---------------|
| < 1.6 mm | 0.10-0.15 mm |
| < 2.4 mm | 0.20 mm |
| < 2.8 mm | 0.25 mm |
| < 3.2 mm | 0.30 mm |

### Backdrill

| Parameter | Capability |
|-----------|------------|
| Backdrill hole size | 0.5-6.5 mm |
| Stub length (to target layer) | < 0.20 mm |
| Depth tolerance | ±0.10 mm |

### Countersink

| Parameter | Capability |
|-----------|------------|
| Special drill angles | 82°, 90°, 120° (hole size 0.3-10 mm) |
| Normal drill angles | 130° (3.175 mm), 165° (3.175-6.5 mm) |
| Angle tolerance | ±0.10° |
| Hole size tolerance | ±0.20 mm |
| Depth tolerance | ±0.15 mm |

---

## Pad Sizes

| Application | Min Pad Size |
|-------------|--------------|
| Via (8 mil), 0.5-1 oz copper | 14 mil (0.35 mm) |
| Via (8 mil), 2 oz copper | 20 mil (0.50 mm) |
| Via (8 mil), 3 oz copper | 24 mil (0.60 mm) |
| BGA pads | 7 mil (0.18 mm) |

**Pad size tolerance:** +5% / -10%

---

## Spacing Requirements

### Hole-to-Trace Clearance

| Board Type | Min Clearance |
|------------|---------------|
| Standard (< 8 layers) | 6 mil |
| Standard (< 14 layers) | 8 mil |
| Standard (< 28 layers) | 9 mil |
| Blind/buried via (2-3 laminations) | 9 mil |

### Surface Finish Dependent Spacing

| Finish/Feature | Min Gap |
|----------------|---------|
| Immersion gold pads | 4 mil |
| Gold fingers | 6 mil |
| HASL pads | 7 mil (10 mil on large copper areas) |
| Legend to pad | 6 mil |
| Peelable solder mask to pad | 16 mil |
| Carbon pads | 15 mil |

### Board Edge Clearance

| Feature | Min Distance |
|---------|--------------|
| Copper to routed edge | 8 mil |
| Inner layer isolation tape | 8 mil min width |

---

## V-Score Clearance (Distance from V-Cut to Copper)

| Board Thickness | 20° | 30° | 45° | 60° |
|-----------------|-----|-----|-----|-----|
| < 1.0 mm | 0.30 mm | 0.33 mm | 0.37 mm | 0.42 mm |
| 1.0-1.6 mm | 0.36 mm | 0.40 mm | 0.50 mm | 0.60 mm |
| 1.6-2.4 mm | 0.42 mm | 0.51 mm | 0.64 mm | 0.80 mm |
| 2.5-3.0 mm | 0.47 mm | 0.59 mm | 0.77 mm | 0.97 mm |

---

## Surface Finishes

### Lead-Free Options

| Finish | Thickness |
|--------|-----------|
| HASL lead-free | 2-40 µm (min 0.4 µm on large areas) |
| Flash Gold | Ni: 2.5-5 µm, Au: > 0.025 µm |
| ENIG | Ni: 2.5-5 µm, Au: 0.05-0.1 µm |
| Immersion Tin | ≥ 1.0 µm |
| Immersion Silver | 0.1-0.3 µm |
| OSP | 0.2-0.3 µm |
| Hard Gold | Au: max 2.5 µm |
| ENEPIG (soldering) | Ni: 3-5 µm, Pd: 0.05-0.1 µm, Au: 0.03-0.05 µm |
| ENEPIG (wire bonding) | Ni: 3-5 µm, Pd: 0.1-0.15 µm, Au: 0.07-0.15 µm |

**Leaded option:** HASL (Tin/Lead)

**Combination finishes:** ENIG+OSP, ENIG+Gold Finger, Flash Gold+Gold Finger, Immersion Silver+Gold Finger, Immersion Tin+Gold Finger

---

## Solder Mask and Legend

| Parameter | Specification |
|-----------|---------------|
| Solder mask thickness (on copper) | 10-18 µm |
| Solder mask thickness (via pads/corners) | 5-8 µm |
| Peelable solder mask thickness | 0.20-0.50 mm |
| Min solder mask bridge (green) | 4 mil |
| Min solder mask bridge (other colors) | 5 mil |
| Min solder mask bridge (2-4 oz copper) | 6 mil |
| Min legend width | 4 mil |
| Min legend height | 23 mil (for 12-18 µm base copper) |

**Solder mask colors:** Green, Yellow, Black, Blue, Red, White, Matte Green

**Legend colors:** White, Yellow, Black

**Legend marking:** Serial number, barcode, QR code (white legend only)

---

## Tolerances

### Dimensional

| Parameter | Tolerance |
|-----------|-----------|
| Outline dimension | ±0.1 mm |
| Outline location | ±0.1 mm |
| Slot routing | ±0.15 mm |
| Blind NPTH slot depth | ±0.10 mm |
| Layer-to-layer registration | < 5 mil |
| Min internal radius | 0.3 mm |

### Board Thickness

| Thickness Range | Tolerance |
|-----------------|-----------|
| < 1.0 mm | ±0.1 mm |
| > 1.0 mm | ±10% |
| Special (< 2.0 mm) | ±0.1 mm |
| Special (2.1-3.0 mm) | ±0.15 mm |

### Impedance

| Target Impedance | Tolerance |
|------------------|-----------|
| < 50 Ω | ±5 Ω |
| ≥ 50 Ω | ±10% (±5% available) |

---

## V-Cut and Panelization

| Parameter | Specification |
|-----------|---------------|
| V-cut angles | 20°, 30°, 45°, 60° |
| Angle tolerance | ±5° |
| Symmetrical tolerance | ±4 mil |
| Remaining thickness tolerance | ±4 mil |
| Outline methods | Routing, V-cut, tab connecting, stamp holes |

---

## Gold Fingers

| Parameter | Specification |
|-----------|---------------|
| Min gap between fingers | 6 mil |
| Chamfer angle tolerance | ±5° |
| Chamfer thickness tolerance | ±5 mil |

---

## Metal Core PCB

| Parameter | Specification |
|-----------|---------------|
| Layer count | 2-4 layers |
| Thermal conductivity | 1-4 W/mK |
| PCB surface finishes | HASL, Flash Gold (< 1 oz), ENIG, Immersion Silver, Immersion Tin, OSP, Hard Gold, ENEPIG |
| Metal base finishes | Cu: Ni+Au plating; Al: Anodic oxidation, hard anodic coating, chemical passivation |
| Technologies | Pre-bonding, post-bonding, agglomerate, metal core, buried metal |

---

## Electrical Testing

| Parameter | Specification |
|-----------|---------------|
| Max test voltage | 500 V |
| Max test current | 200 mA |

---

## HDI Stackup Options

| Type | Description |
|------|-------------|
| 1+n+1 | Single buildup layer each side |
| 1+1+n+1+1 | Two buildup layers each side |
| 2+n+2 | Two buildup layers with buried vias (RCC only, buried via < 0.3 mm) |

**Via fill options:** Resin fill, copper fill

---

## Production Technologies

Backplane, HDI, blind and buried via, embedded capacitance, embedded resistance, thick copper, backdrill

---

## Flex PCB Capabilities

For flexible circuit specifications, see [Flex PCB Capability Limits](/technical-library/flex-pcb-capability-limits/)

---

## Related Articles

- [PCB Designer's Tips](/technical-library/pcb-designers-help/) – Design guidelines and cost optimization
- [PCB Materials and Laminates Guide](/technical-library/pcb-materials-guide/) – Material specifications and data sheets
- [Flex PCB Capability Limits](/technical-library/flex-pcb-capability-limits/) – Flexible circuit specifications
- [How Multilayer PCBs Are Made](/technical-library/how-to-build-pcbs/) – Understanding the fabrication process

---

**Questions about capabilities for your design?** [Request a quote](/quote/) – we'll review your requirements and confirm feasibility.

---

<a id="pcb-component-cooling"></a>

## PCB Component Cooling with Thermal Vias

## The Problem: Heat Trapped Under Components

Power semiconductors, voltage regulators, and LED drivers generate significant heat. If that heat can't escape through the PCB, junction temperatures rise, reliability drops, and components fail early.

Standard PCBs are poor thermal conductors—FR-4 has thermal conductivity around 0.3 W/m·K, compared to 400 W/m·K for copper. But you can dramatically improve heat transfer by adding thermal vias: dense arrays of plated through-holes that conduct heat from the component side to inner planes or the opposite surface.

## How Thermal Vias Work

Plated through-holes are essentially copper tubes through the PCB. Copper's high thermal conductivity creates a heat path through the otherwise insulating laminate.

The effectiveness depends on:
- **Via density** – more vias = more heat transfer
- **Via diameter** – larger vias have more copper area
- **Plating thickness** – thicker copper = lower thermal resistance
- **Fill material** – filled vias transfer more heat than hollow ones

## Optimal Via Pattern

For maximum thermal performance, use a staggered hex pattern:

1. **Drill diameter**: 0.5 mm (finished ~0.4 mm after plating)
2. **Row pitch (X)**: 0.7 mm minimum (maintains 0.2 mm substrate between holes)
3. **Row offset (Y)**: 0.6 mm
4. **Stagger**: Offset alternate rows by half the X pitch
5. **Repeat pitch (Y)**: 1.2 mm for the full pattern

**Minimum copper plating**: 25 µm—more is better if your process allows.

![Grid diagram showing via hole patterns at different densities from 1×1 mm to 10×10 mm spacing, with corresponding via counts and copper area calculations](/assets/images/technical-library/bild15.webp)

*Via density comparison: tighter patterns provide more thermal transfer but increase drilling cost*

## Design Trade-offs

### Via Size vs. Density

| Via Diameter | Pitch | Vias per cm² | Relative Thermal Performance |
|--------------|-------|--------------|------------------------------|
| 0.3 mm | 0.5 mm | 400 | Highest (but expensive) |
| 0.4 mm | 0.7 mm | 200 | Good balance |
| 0.5 mm | 0.9 mm | 120 | Cost-effective |
| 0.6 mm | 1.0 mm | 100 | Standard approach |

![Cross-section diagram showing thermal via construction with copper plating thickness and filled via option](/assets/images/technical-library/bild24.webp)

*Thermal via cross-section: plating thickness directly affects heat transfer capacity*

### Filled vs. Hollow Vias

- **Hollow vias**: Standard process, lower cost, adequate for moderate heat loads
- **Filled vias**: Conductive or non-conductive fill, better thermal performance, required for via-in-pad under thermal components
- **Capped vias**: Filled and plated over, flat surface for component mounting

![Comparison of different thermal via configurations showing hollow, filled, and capped options](/assets/images/technical-library/bild32.webp)

*Via fill options: choose based on thermal requirements and component mounting needs*

## Thermal Via Placement

### Under Exposed Pads
Most power components have an exposed thermal pad on the bottom. Place a dense via array directly under this pad, connecting to inner ground planes or a bottom-side heat sink area.

### Connection to Planes
Thermal vias should connect to large copper areas—either inner planes or external copper pours. The plane acts as a heat spreader, distributing heat across a larger area.

### Keep-Out Considerations
Don't place thermal vias:
- Under solder paste areas (solder wicks into unfilled vias)
- Too close to signal vias (thermal cycling stress)
- Where they interfere with inner layer routing

## Alternative Approaches

For extreme thermal requirements, consider:

- **Metal-core PCBs (MCPCB)** – aluminium or copper substrate
- **Insulated metal substrate (IMS)** – thin dielectric on metal base
- **Embedded heat pipes** – for localised hot spots
- **Thick copper** – 2 oz and above for better lateral spreading

## When to Use Thermal Vias

Thermal vias are appropriate when:

- Component dissipation exceeds ~0.5 W in a small area
- Junction temperature margins are tight
- The component has an exposed thermal pad
- Standard FR-4 construction is otherwise acceptable

For detailed specifications, see the [PCB Component Cooling PDF](/assets/pdfs/PCB-Component-Cooling.pdf).

---

## Related Articles

- [How Multilayer PCBs Are Made](/technical-library/how-to-build-pcbs/) – Understanding plating and drilling for thermal vias
- [Multilayer PCB Capabilities](/technical-library/pcb-capability-limits/) – Hole size and copper weight specifications
- [PCB Materials and Laminates Guide](/technical-library/pcb-materials-guide/) – Thermal conductivity of different materials

---

**Need thermal management in your PCB?** [Request a quote](/quote/) – we can advise on via patterns and material selection for heat dissipation.

---

<a id="pcb-materials-guide"></a>

## PCB Materials and Laminates Guide

## The Problem: Choosing the Right Laminate

Every PCB design starts with a materials decision that affects cost, performance, and reliability. Choose standard FR-4 for an RF application and you'll fight signal loss. Specify exotic materials for a simple digital board and you'll waste budget. The challenge is matching material properties - dielectric constant, loss tangent, thermal stability - to your actual requirements.

This guide provides the specifications you need to make informed laminate decisions, organised by application with links to manufacturer data sheets.

## Evidence From Supplied Boards

Our supplied-job records include more than 1,800 high-Tg projects and more than 400 projects using a named RF or microwave laminate. Rogers-family materials are the most common named RF laminates in that history, with supplied experience also covering Panasonic Megtron, Isola, ITEQ, and hybrid RF/FR-4 stackups.

These rounded counts are historical delivery evidence, not a live stock list. Exact laminate availability, constructions, minimum order quantities, and lead times are confirmed during technical review. If an exact material is unavailable, provide the electrical, thermal, mechanical, and compliance requirements that must remain unchanged so a suitable alternative can be evaluated.

## Key Material Properties

Understanding these properties helps you select the right laminate:

- **Dk (Dielectric Constant)** - Determines impedance and signal velocity. Lower Dk = faster signals, easier impedance control
- **Df (Dissipation Factor)** - Signal loss per unit length. Critical above 1 GHz; lower is better
- **CTE (Coefficient of Thermal Expansion)** - Dimensional change with temperature. Z-axis CTE affects via reliability
- **Tg (Glass Transition Temperature)** - Temperature where the laminate softens. Must exceed reflow temperatures for lead-free assembly
- **Td (Decomposition Temperature)** - Where the material begins to break down chemically

## Material Selection by Data Rate

| Data Rate | Target Df @ 10 GHz | Material Class | Examples |
|-----------|-------------------|----------------|----------|
| ≤25 Gbps | ~0.010 | Mid-loss FR-4 | Isola 370HR, standard high-Tg |
| 56 Gbps PAM4 | 0.004-0.005 | Low-loss | Megtron 6, I-Tera MT40 |
| 112 Gbps PAM4 | ≤0.002 | Ultra-low-loss | Megtron 7/8, Tachyon 100G, IT-988GSE |
| 224 Gbps PAM4 | ≤0.0015 | Extreme-low-loss | Megtron 8, TerraGreen 400G |

---

## Standard FR-4 Materials

| Material | Dk @ 10 GHz | Df @ 10 GHz | Tg °C | Td °C | CTE Z (pre-Tg) | Data Sheet |
|----------|-------------|-------------|-------|-------|----------------|------------|
| **Standard FR-4 Tg 135** | 4.3-4.5 | 0.018-0.020 | 140 | 305-315 | 55-70 ppm/°C | [S1141 FR-4](/assets/pdfs/e8f6628e-s1141.pdf) |
| **FR-4 Tg 150** | 4.2-4.4 | 0.015-0.018 | 155 | 330-348 | 50-65 ppm/°C | [S1000/S1000B](/assets/pdfs/66760f93-s1000-s1000b.pdf) |
| **Isola FR406 Tg 170** | 3.92 | 0.0172 | 170 | 300 | 60 ppm/°C | [S1000-2 & Prepreg](/assets/pdfs/s1000-2.pdf) |
| **Isola 370HR Tg 180** | 3.92 | 0.0250 | 180 | 340 | 45 ppm/°C | [Isola Product Guide (PDF)](https://www.isola-group.com/wp-content/uploads/Isola_Product_Guide_Online-9-27-2022.pdf) |
| **Isola FR408** | 3.65 | 0.0125 | 180 | 360 | 60 ppm/°C | [Isola Product Guide (PDF)](https://www.isola-group.com/wp-content/uploads/Isola_Product_Guide_Online-9-27-2022.pdf) |
| **Isola G200 BT-Epoxy** | 3.65 | 0.0150 | 180 | 325 | 55 ppm/°C | [G200 Data Sheet](/assets/pdfs/G200-Epoxy-Laminate-and-Prepreg-Data-Sheet-Isola.pdf) |

---

## Low-Loss Materials (High-Speed Digital)

These materials target 10-56 Gbps applications where standard FR-4 causes unacceptable signal loss.

| Material | Dk @ 10 GHz | Df @ 10 GHz | Tg °C | Target Application | Data Sheet |
|----------|-------------|-------------|-------|-------------------|------------|
| **Isola I-Tera MT40** | 3.38-3.75 (options) | 0.0028-0.0035 | 215 | High-speed backplanes | [I-Tera MT40 (PDF)](https://www.isola-group.com/wp-content/uploads/data-sheets/i-tera-mt40.pdf) / [Dk/Df Tables](https://www.isola-group.com/wp-content/uploads/data-sheets/I-Tera_sup_____sup__MT40__Dk_Df_Tables.pdf) |
| **Panasonic Megtron 6** | 3.37-3.61 (varies by glass) | 0.004 | 185-210 | 25-56 Gbps digital | [R-5775 (PDF)](https://industrial.panasonic.com/content/data/EM/PDF/ipcdatasheet_R-5775.pdf) / [Low-Dk Glass (PDF)](https://industrial.panasonic.com/cdbs/www-data/pdf/EMB0000/ast-ind-232629.pdf) |
| **Panasonic Megtron 7** | 3.6 @ 1 GHz | 0.0015 @ 1 GHz | 200 | 56-112 Gbps, HDI | [R-5785 (PDF)](https://industrial.panasonic.com/content/data/EM/PDF/DataS_MEGTRON7_R-5785_en_2022.pdf) / [50 GHz Data (PDF)](https://bayareacircuits.com/wp-content/uploads/2020/05/MDS_Panasonic_Meg7.pdf) |
| **Doosan DS-7409DV** | 3.62 | 0.0035 | High | Halogen-free high-speed | [DS-7409 (PDF)](https://www.mclpcb.com/wp-content/uploads/2021/05/doosan-ds-7409.pdf) |
| **TUC ThunderClad 2** | Low-loss | Low-loss | High | High-speed digital | [TU-883 (PDF)](https://www.hemeixinpcb.com/images/pdf/TUC/TU-883_thunderclad%202_datasheet.pdf) |
| **TUC ThunderClad 3+** | Ultra-low | Ultra-low | High | 56G+ applications | [TU-933 (PDF)](https://www.hemeixinpcb.com/images/pdf/TUC/TU-933_thunderclad%203+_datasheet.pdf) |

**Note on Megtron 6:** Dk varies significantly with glass style - 1035 glass (65% resin) gives Dk 3.37, while 2116 glass (54% resin) gives Dk 3.61. Specify construction when quoting.

---

## Ultra-Low-Loss Materials (112G+ PAM4)

For AI servers, 800 GbE switches, and next-generation data centre applications.

| Material | Dk @ 10 GHz | Df @ 10 GHz | Tg °C | Notes | Data Sheet |
|----------|-------------|-------------|-------|-------|------------|
| **Panasonic Megtron 8 (R-5795)** | 3.1 | 0.0012 | 220 | 30% lower loss than Megtron 7 | [R-5795 (PDF)](https://industrial.panasonic.com/content/data/EM/PDF/DataS_MEG8S_MEG8_R-5795S_R-5795_en_202407.pdf) / [Press Release](https://news.panasonic.com/global/press/data/2022/01/en220118-4/en220118-4.pdf) |
| **Isola TerraGreen 400G** | 3.05-3.15 | 0.0018 | N/A | Halogen-free | [Product Page](https://www.isola-group.com/pcb-laminates-prepreg/terragreen-400g/) |
| **Isola TerraGreen 400GE** | 3.15 | 0.0018 | N/A | Halogen-free | [TerraGreen 400GE (PDF)](http://test.isola-group.com/wp-content/uploads/data-sheets/terragreen-400ge.pdf) |
| **Isola Tachyon 100G** | 3.02 | 0.0021 | 220 (DMA) | Established 100G+ material | [Tachyon 100G (PDF)](https://www.isola-group.com/wp-content/uploads/data-sheets/tachyon-100g-laminate-and-prepreg.pdf) |
| **ITEQ IT-988GSE** | 3.28 @ 28 GHz | 0.0016 @ 28 GHz | >230 | Halogen-free, low-Dk glass | [IT-988GSE (PDF)](https://www.hemeixinpcb.com/images/pdf/ITEQ/IT-988G-SE-Datasheet.pdf) |
| **ITEQ IT-988G** | 3.3 | 0.002 | >200 | High-speed digital | [IT-988G (PDF)](https://www.mclpcb.com/wp-content/uploads/2021/05/ITEQ-IT-988G-Datasheet.pdf) |

---

## RF and Microwave Materials

### Rogers Thermoset (RO4000 Series)

These hydrocarbon-ceramic materials process like FR-4 but offer RF performance. **Note:** RO4000 materials are thermoset and do not have a traditional Tg.

| Material | Dk @ 10 GHz | Df @ 10 GHz | CTE (X;Y;Z) | Best For | Data Sheet |
|----------|-------------|-------------|-------------|----------|------------|
| **Rogers RO4003C** | 3.38 (process) / 3.55 (design) | 0.0027 | 11;14;46 | Lowest loss, general RF | [RO4003C/RO4350B (PDF)](https://rogerscorp.com/-/media/project/rogerscorp/documents/advanced-electronics-solutions/english/data-sheets/ro4000-laminates-ro4003c-and-ro4350b---data-sheet.pdf) / [Product Page](https://www.rogerscorp.com/advanced-electronics-solutions/ro4000-series-laminates/ro4003c-laminates) |
| **Rogers RO4350B** | 3.48 (process) / 3.66 (design) | 0.0037 | 14;16;32 | UL 94 V-0 needed | [RO4003C/RO4350B (PDF)](https://rogerscorp.com/-/media/project/rogerscorp/documents/advanced-electronics-solutions/english/data-sheets/ro4000-laminates-ro4003c-and-ro4350b---data-sheet.pdf) / [Product Page](https://rogerscorp.com/advanced-electronics-solutions/ro4000-series-laminates/ro4350b-laminates) |
| **Rogers RO4835** | 3.48 | 0.0031 | Similar | High oxidation resistance | [RO4000 Series](https://www.rogerscorp.com/advanced-electronics-solutions/ro4000-series-laminates) |
| **Rogers RO4450F Bondply** | 3.23 | 0.004 | 16;19;80 | Bonding RO4000 cores | [RO4400 Bondply (PDF)](https://rogerscorp.com/-/media/project/rogerscorp/documents/advanced-electronics-solutions/english/data-sheets/ro4400-series-bondply-data-sheet---ro4450f-and-ro4460g2-bondply.pdf) |

**Fabrication Resource:** [RO4000 Series Processing Guide (PDF)](https://rogerscorp.com/-/media/project/rogerscorp/documents/advanced-electronics-solutions/english/fabrication-information/fabrication-guidelines-ro4000-series-ro4003cro4350bro4835-laminates.pdf)

### PTFE and Ceramic-Filled Materials

| Material | Dk | Df | Test Freq | Notes | Data Sheet |
|----------|-----|------|-----------|-------|------------|
| **Rogers RO3003** | 3.00 | 0.0010 | 10 GHz | Industry standard for 77 GHz radar | [RO3000 Series (PDF)](https://rogerscorp.com/-/media/project/rogerscorp/documents/advanced-electronics-solutions/english/data-sheets/ro3000-laminate-data-sheet-ro3003----ro3006----ro3010----ro3035.pdf) |
| **Rogers RO3003G2** | 3.07 (design) | Low | 10 GHz | Optimised for ADAS | [RO3003G2 (PDF)](https://www.rogerscorp.com/-/media/project/rogerscorp/documents/advanced-electronics-solutions/english/data-sheets/ro3003g2--data-sheet.pdf) / [Product Page](https://www.rogerscorp.com/advanced-electronics-solutions/ro3000-series-laminates/ro3003g2-laminates) |
| **Rogers RO3000 Bondply** | Varies | Varies | 10 GHz | Bonding RO3000 cores | [RO3000 Bondply (PDF)](https://rogerscorp.com/-/media/project/rogerscorp/documents/advanced-electronics-solutions/english/data-sheets/ro3000-series-bondply--data-sheet--processing-guidelines.pdf) |
| **Taconic RF-35** | 3.50 | 0.0018 | 1.9 GHz | PTFE-based, now AGC Multi Material | [RF-35 (PDF)](https://www.multi-circuit-boards.eu/fileadmin/pdf/leiterplatten_material/e_taconic_rf35-hf_www.multi-circuit-boards.eu.pdf) |
| **Taconic RF-35TC** | 3.50 | 0.0018 | 1.9 GHz | Thermally conductive variant | [RF-35TC (PDF)](https://www.agc-multimaterial.com/agc-downloads/AGC_RF-35TC_TDS.pdf) |
| **Rogers DiClad 522/527/870/880** | 2.5-2.65 | 0.0018-0.0022 | 10 GHz | PTFE/glass, various Dk options | [DiClad Series (PDF)](https://rogerscorp.com/-/media/project/rogerscorp/documents/advanced-electronics-solutions/english/data-sheets/diclad-series-data-sheet.pdf) / [Product Page](https://www.rogerscorp.com/advanced-electronics-solutions/diclad-series-laminates) |
| **Rogers RT/duroid 5870/5880** | 2.2-2.33 | 0.0009-0.0012 | 10 GHz | Lowest Dk PTFE | [RT/duroid 5870/5880 (PDF)](https://rogerscorp.com/-/media/project/rogerscorp/documents/advanced-electronics-solutions/english/data-sheets/rt-duroid-5870---5880-data-sheet.pdf) / [Product Page](https://www.rogerscorp.com/advanced-electronics-solutions/rt-duroid-laminates) |
| **Rogers RT/duroid 6006/6010** | 6.15-10.2 | 0.0019-0.0023 | 10 GHz | High-Dk for miniaturisation | [RT/duroid 6006/6010 (PDF)](https://www.rogerscorp.com/-/media/project/rogerscorp/documents/advanced-electronics-solutions/english/data-sheets/rt-duroid-6006-6010lm-laminate-data-sheet.pdf) |

---

## 77 GHz Automotive Radar Materials

The automotive radar market has driven significant material innovation. These materials target 76-81 GHz ADAS applications.

| Material | Manufacturer | Dk @ 77 GHz | Insertion Loss | Data Sheet |
|----------|--------------|-------------|----------------|------------|
| **RO3003** | Rogers | 3.00 | ~1.3 dB/inch | [RO3000 Series (PDF)](https://rogerscorp.com/-/media/project/rogerscorp/documents/advanced-electronics-solutions/english/data-sheets/ro3000-laminate-data-sheet-ro3003----ro3006----ro3010----ro3035.pdf) |
| **RO3003G2** | Rogers | 3.07 (design) | Low | [RO3003G2 (PDF)](https://www.rogerscorp.com/-/media/project/rogerscorp/documents/advanced-electronics-solutions/english/data-sheets/ro3003g2--data-sheet.pdf) |
| **RO4830 Plus** | Rogers | 3.03 | 1.5 dB/inch | [Rogers Downloads](https://www.rogerscorp.com/downloads) |
| **mmWave77** | Shengyi | 3.06 (design) | 1.29 dB/inch | [mmWave77 (PDF)](https://www.syst.com.cn/uploadfiles/2024/07/20240722163501708.pdf) / [Alternate (PDF)](https://www.nwengineeringllc.com/files/datasheets/Shengyi-mmWave77.pdf) |
| **Astra MT77** | Isola | 3.0 | Low | [Astra MT77 (PDF)](https://www.isola-group.com/wp-content/uploads/data-sheets/astra-mt77.pdf) / [Dk/Df Tables](https://www.isola-group.com/wp-content/uploads/data-sheets/astra-mt77-laminate-and-prepreg__Dk_Df_Tables.pdf) |
| **PegaClad** | TUC | Low-Dk | Low | [Product Page](https://www.tuc.com.tw/en-us/products-detail/id/43/index/4/title/PegaClad_Series) |

**Design Resource:** [Rogers Autonomous Driving Design eBook (PDF)](https://rogerscorp.com/-/media/project/rogerscorp/documents/advanced-electronics-solutions/english/general/autonomous-driving-design-technology-ebook.pdf)

---

## Polyimide and High-Temperature Materials

| Material | Dk @ 1 GHz | Df @ 1 GHz | Tg °C | Application | Data Sheet |
|----------|------------|------------|-------|-------------|------------|
| **Arlon 85NT** | 3.7 | 0.015 | 280 | Flex, high-temp | [Arlon 85NT](/assets/pdfs/85NT.pdf) |
| **Arlon 55NT** | 3.9 | 0.018 | 259 | Thermount reinforced | [Arlon 55NT](/assets/pdfs/55NT.pdf) |

**Note:** Arlon EMD (PCB laminates) is now owned by Elite Material Co. (Taiwan) as of January 2021. Products continue manufacturing in Rancho Cucamonga, CA.

---

## Thermal Management Substrates

| Material | Dk | Thermal Conductivity | Application | Data Sheet |
|----------|-----|---------------------|-------------|------------|
| **Bergquist HPL-03015** | 6.6 @ 1 MHz | High | LED lighting, power | [HPL-03015](/assets/pdfs/PDS_HPL_0414-v6.pdf) |
| **ITEQ IT-170GRA1** | N/A | ≥3.0 W/m·K | Halogen-free thermal | [IT-170GRA1 (PDF)](https://www.mclpcb.com/wp-content/uploads/2021/05/ITEQ-IT-170GRA1-Data-sheet-rev-1.0-17-Data-Sheet.pdf) |

**Note:** Bergquist is now LOCTITE Bergquist (Henkel). Focus is thermal interface materials rather than conventional PCB laminates.

---

## Material Manufacturers

### Major Global Suppliers

| Manufacturer | Specialty | Resources |
|--------------|-----------|-----------|
| **Rogers Corporation** | High-frequency PTFE, thermoset, radar materials | [Website](https://www.rogerscorp.com) / [Downloads](https://www.rogerscorp.com/downloads) / [Laminate Comparison Tool](https://www.rogerscorp.com/advanced-electronics-solutions) |
| **Isola Group** | FR-4, low-loss, ultra-low-loss laminates | [Website](https://www.isola-group.com) / [Product Guide (PDF)](https://www.isola-group.com/wp-content/uploads/Isola_Product_Guide_Online-9-27-2022.pdf) |
| **Panasonic** | Megtron series low-loss materials | [Website](https://industry.panasonic.eu/products/devices/electronic-materials/circuit-board-materials/multi-layer-circuit-board-materials-ict-infrastructure-equipment-megtron-series) |
| **AGC Multi Material** | Taconic PTFE, Nelco products | [Website](https://www.agc-multimaterial.com) / [About](https://www.agc-multimaterial.com/company/) |
| **DuPont** | Pyralux flex materials | [Website](https://www.dupont.com) |

### Asian Suppliers (Now Competitive in Premium Segments)

| Manufacturer | Specialty | Resources |
|--------------|-----------|-----------|
| **Shengyi (SYTECH)** | mmWave77 for 77 GHz radar, world's #2 CCL manufacturer | [Website](http://www.syst.com.cn) / [Shengyi USA](https://www.shengyi-usa.com/) / [RF Products](https://www.shengyi-usa.com/rf-and-microwave/) |
| **ITEQ Corporation** | IT-988GSE ultra-low-loss, high-speed digital | [Website](https://www.iteq.com.tw) / [Products](https://www.iteq.com.tw/product/) |
| **TUC** | PegaClad for Sub-6G and 77 GHz, ThunderClad | [Website](https://www.tuc.com.tw/index) |
| **Elite Material (EMC)** | High-speed laminates, owns Arlon EMD | [Website](https://www.emctw.com) |
| **Doosan Electro-Materials** | DS-7409 series, PTFE mmWave materials | [Website](https://www.doosanelectromaterials.com/en/) |
| **Nan Ya Plastics** | Vertically integrated, world's #4 CCL maker | [Website](http://www.nanyaplastics.com.tw) |

### Supplier Status Notes

- **Park Electrochemical** exited the PCB materials business in July 2018. Now Park Aerospace (aerospace composites only).
- **Taconic** and **Nelco** are now both part of AGC Multi Material. Product names are retained.
- **Arlon** was split: EMD division (PCB laminates) sold to Elite Material (Taiwan); silicone products remain with Rogers.
- **Bergquist** acquired by Henkel in 2014, now LOCTITE Bergquist (thermal TIMs only).
- **Laird Performance Materials** acquired by DuPont, now branded as Qnity.

---

## Material Databases

These third-party resources aggregate datasheets from multiple manufacturers:

| Resource | Description |
|----------|-------------|
| [CircuitData Material Database](https://materials.circuitdata.org/) | Open-source database with 700+ materials |
| [everythingRF Laminates](https://www.everythingrf.com/search/laminates) | RF-focused material database |

---

## Prepreg Specifications

![Prepreg specification table showing glass styles, resin content, and thickness options](/assets/images/technical-library/5026d749-prepreg-spec.webp)

*Standard prepreg specifications for common glass styles*

## Glass Weaves and Copper Thicknesses

![Chart showing different glass fibre weave types alongside standard copper foil thickness options](/assets/images/technical-library/68d720e2-prepreg-copper.webp)

*Glass fibre weave types (left) and standard copper thicknesses (right)*

### Spread Glass Technology

For data rates above 10 Gbps, glass weave effects become significant. Spread glass technology flattens fibre bundles, creating more uniform resin distribution and reducing the Dk difference between glass-rich and resin-rich regions. This reduces **glass-weave skew** that causes timing problems in high-speed differential pairs.

Isola I-Tera MT40 is available exclusively with spread glass constructions.

---

## Microwave Material Selection

For detailed RF/microwave substrate selection guidance, see our **[RF and Microwave PCB Substrate Selection Guide](/technical-library/rf-microwave-substrate-selection/)** - covering frequency thresholds, PTFE processing requirements, hybrid stackup strategies, and application-specific recommendations.

---

## When to Choose Each Material Class

**Standard FR-4 (Tg 135-150):**
- Digital designs below 1 GHz
- Cost-sensitive applications
- Standard lead-free assembly

**High-Tg FR-4 (Tg 170+):**
- Multiple reflow cycles
- Automotive and industrial (operating temps to 125°C)
- Improved via reliability for thick boards (>2 mm)

**Low-Loss (Megtron 6, I-Tera MT40):**
- 10-56 Gbps digital signalling
- Backplanes and high-layer-count designs
- Cost-performance balance

**Ultra-Low-Loss (Megtron 7/8, Tachyon, TerraGreen):**
- 112 Gbps+ PAM4 signalling
- AI servers and 800 GbE switches
- Where Df ≤0.002 is required

**Rogers/Taconic PTFE:**
- RF and microwave above 6 GHz
- Low-loss transmission lines
- Tight Dk tolerance requirements

**Rogers RO4000 Series:**
- RF applications requiring FR-4-like processing
- Mixed RF/digital boards
- When PTFE processing is impractical

**Polyimide:**
- Flex and rigid-flex designs
- High-temperature environments (>150°C continuous)
- Aerospace and defence

---

## Frequently Asked Questions

### What Dk value should I use for impedance calculations?

Use the Dk value measured at the frequency closest to your operating frequency. FR-4's Dk varies from ~4.5 at 1 MHz to ~4.2 at 10 GHz. For RF designs, use materials with Dk specified at 10 GHz. Rogers provides both "process" Dk (for manufacturing) and "design" Dk (for simulation) - use the design value for impedance calculations.

### When do I need high-Tg FR-4?

High-Tg materials (170°C+) are required for lead-free assembly with multiple reflow cycles, thick boards (over 2 mm) where via stress is higher, and automotive applications with operating temperatures up to 125°C per AEC-Q standards.

### What happened to Arlon? Is it still separate from Rogers?

Arlon was split. Rogers acquired Arlon LLC in January 2015 and retained the silicone products. The PCB laminate division (Arlon EMD) was sold separately and is now owned by Elite Material Co. (EMC) of Taiwan as of January 2021. Arlon EMD continues manufacturing polyimide and high-Tg materials in Rancho Cucamonga, CA.

### Are Nelco and Taconic materials still available?

Yes. AGC Inc. (Japan) acquired Park Electrochemical's Nelco brand in December 2018 and Taconic in June 2019. Both product lines continue under AGC Multi Material with original product names retained.

### Is Megtron 6 obsolete now that Megtron 7 and 8 exist?

No. Megtron 6 remains widely used and is not superseded. It offers excellent performance (Df ~0.004 @ 10 GHz) at lower cost than Megtron 7/8 and is appropriate for many high-speed applications below 112 Gbps.

### What are the best materials for 77 GHz automotive radar?

Leading materials include Rogers RO3003/RO3003G2 (industry standard), the new Rogers RO4830 Plus (2025, thermoset option), Shengyi mmWave77 (cost-competitive alternative), and Isola Astra MT77 (FR-4 process compatible).

### Which Asian suppliers match Rogers/Isola for premium applications?

Shengyi (mmWave77), ITEQ (IT-988GSE), Doosan (DS-7409 series), and TUC (PegaClad) now offer materials genuinely competitive with Western suppliers for high-frequency and high-speed digital applications. About 70% of high-speed CCL production is now based in Asia.

### What Df is required for 112 Gbps PAM4 signalling?

Target Df ≤0.002 @ 10 GHz. Suitable materials include Megtron 8 (Df 0.0012), TerraGreen 400G (Df 0.0018), and Tachyon 100G (Df 0.0021).

### What's the difference between Tg and Td?

Tg (glass transition) is where the material softens but remains structurally intact - the board can still function. Td (decomposition) is where chemical breakdown begins. Your operating and processing temperatures must stay well below both. Note that Rogers RO4000 series materials are thermoset and do not have a traditional Tg.

### What are the halogen-free requirements?

Per IEC 61249-2-21: Chlorine ≤900 ppm, Bromine ≤900 ppm, Total Cl+Br ≤1500 ppm. While not mandatory everywhere, halogen-free materials are increasingly specified. Options include Isola TerraGreen series, ITEQ IT-988GSE, and Doosan DS-7409DV.

---

## Related Articles

- [RF and Microwave PCB Fabrication](/rf-microwave-pcb-fabrication/) - Delivered Rogers-family and hybrid RF/FR-4 experience
- [RF and Microwave PCB Substrate Selection](/technical-library/rf-microwave-substrate-selection/) - Detailed RF material guidance with frequency thresholds
- [Controlled Impedance PCB Design](/technical-library/controlled-impedance-pcb-design/) - How dielectric constant affects impedance
- [RoHS Effect on PCBs](/technical-library/rohs-effect-on-pcbs/) - Tg requirements for lead-free assembly
- [Multilayer PCB Capabilities](/technical-library/pcb-capability-limits/) - Material options in our capability table

---

**Need help selecting materials?** [Request a quote](/quote/) - we'll recommend the best laminate for your electrical and thermal requirements.

---

<a id="rf-microwave-substrate-selection"></a>

## RF and Microwave PCB Substrate Selection Guide

## The Problem: Material Choice Makes or Breaks RF Designs

Standard FR-4 works fine for digital circuits, but RF and microwave designs demand more. Above 1 GHz, FR-4's high loss tangent (Df ~0.02) attenuates signals noticeably. By 10 GHz, you're losing over 1 dB per inch. Worse, FR-4's dielectric constant varies unpredictably with frequency and temperature, making impedance control unreliable.

For engineers designing at microwave frequencies, this creates a genuine problem: how do you choose from dozens of specialty materials with overlapping specifications and wildly different costs?

## The Solution: Match Material Category to Your Frequency and Application

RF substrate materials fall into distinct categories, each suited to specific frequency ranges and applications. Understanding these categories simplifies selection considerably.

**Key benefits of proper material selection:**

- Predictable impedance control across production volumes
- Acceptable insertion loss at your operating frequency
- Thermal stability for outdoor and power applications
- Manufacturing processes your fabricator can actually handle
- Cost optimisation through hybrid stackup strategies

The right material balances electrical performance against manufacturing complexity. The "best" material electrically often creates fabrication challenges that increase cost and risk.

## Evidence From Supplied RF and Microwave Boards

Our production history includes more than 400 projects using a named RF or microwave laminate and hundreds using Rogers-family materials, including RO4350 and RO4003 constructions. Supplied combinations include:

- RF laminates with blind and/or buried vias
- RF laminates with controlled impedance
- Hybrid RF/FR-4 stackups
- Explicitly identified PTFE-family laminates

These rounded figures and material families describe delivered jobs. Material names elsewhere in this guide are technical selection references, not blanket statements of current stock or availability. We confirm the exact material and stackup for each quote. If an exact laminate is unavailable, send the operating frequency, Dk/Df targets, thermal requirements, approvals, and preferred construction so an application-specific alternative can be evaluated.

## Material Categories at a Glance

| Category | Dk Range | Df @ 10 GHz | Processing | Cost vs FR-4 | Best For |
|----------|----------|-------------|------------|--------------|----------|
| Standard FR-4 | 4.3-4.7 | 0.018-0.020 | Standard | 1× | Below 1 GHz |
| Hydrocarbon ceramic (RO4000) | 3.38-3.66 | 0.0027-0.0037 | FR-4 compatible | 3-5× | 500 MHz - 15 GHz |
| Ceramic-filled PTFE (RO3000) | 3.0-10.2 | 0.0010-0.0023 | Specialised | 5-7× | 15-77 GHz, radar |
| Pure/glass PTFE (RT/duroid) | 2.1-2.65 | 0.0009-0.0018 | Most difficult | 8-10× | Satellite, lowest loss |
| Advanced thermoset (Astra MT77) | 3.0 | 0.0017 | FR-4 compatible | 3-5× | mmWave with easier processing |

---

## Frequency Determines When Material Choice Becomes Critical

FR-4 has a practical ceiling of 1-2 GHz for RF work. Beyond this, Dk instability and dielectric loss become limiting factors.

| Frequency Range | Viable Materials | Key Constraint |
|-----------------|------------------|----------------|
| DC - 1 GHz | Standard FR-4 | Cost dominates |
| 1 - 5 GHz | Enhanced FR-4, RO4000 series | Dk stability |
| 5 - 20 GHz | RO4350B, RO3003, Astra MT77 | Dielectric loss |
| 20 - 40 GHz | RO3003, RT/duroid 5880 | Dk tolerance, Df |
| 40 - 77 GHz | RO3003, RT/duroid 5880, Astra MT77 | All properties critical |
| Above 77 GHz | PTFE, advanced thermosets | Specialised design |

The crossover from conductor-dominated to dielectric-dominated loss occurs between 1-10 GHz for most materials. Above this range, material Df directly limits system performance.

---

## PTFE-Based Materials: Lowest Loss, Highest Complexity

Pure and glass-reinforced PTFE materials offer Dk values of 2.1-2.65 and Df as low as 0.0009 - the lowest dielectric loss available in commercial laminates. Rogers RT/duroid 5880, with Df of 0.0009 at 10 GHz, represents the gold standard for phase-sensitive applications like phased arrays and satellite communications.

However, PTFE's soft, non-stick properties create significant fabrication challenges. Not all PCB fabricators can process these materials.

### PTFE Processing Requirements

| Process Step | Requirement |
|--------------|-------------|
| Drilling | 180,000-250,000 RPM, slow feed (20-60 µm/rev), fresh carbide bits |
| Surface prep | Plasma treatment or sodium naphthalene etch |
| Plating | Thorough bakeout (115-125°C, 15-30 min) before copper |
| Solder mask | Apply within 12 hours of etching |
| Routing | Diamond-coated or carbide tools |

Drill bits should not be resharpened - ceramic fillers damage cutting edges after 2,000-3,000 hits.

### PTFE and Ceramic-Filled Materials

| Material | Dk @ 10 GHz | Df @ 10 GHz | Construction | CTE ppm/°C (X;Y;Z) | Best For |
|----------|-------------|-------------|--------------|-------------------|----------|
| RT/duroid 5870 | 2.33 | 0.0012 | Glass PTFE | 22;28;173 | Low-loss, phase stable |
| RT/duroid 5880 | 2.20 | 0.0009 | Glass PTFE | 31;48;237 | Lowest Df available |
| RT/duroid 6002 | 2.94 | 0.0012 | Ceramic PTFE | 16;16;24 | High reliability, aerospace |
| RT/duroid 6006 | 6.15 | 0.0019 | Ceramic PTFE | 17;17;24 | Circuit miniaturisation |
| RT/duroid 6010LM | 10.2 | 0.0023 | Ceramic PTFE | 24;24;24 | Maximum miniaturisation |
| RO3003 | 3.00 | 0.0010 | Ceramic PTFE | 17;17;24 | 77 GHz radar standard |
| RO3006 | 6.15 | 0.0020 | Ceramic PTFE | 17;17;24 | High-Dk applications |
| RO3010 | 10.2 | 0.0022 | Ceramic PTFE | 13;11;16 | Tight CTE match |

---

## Ceramic-Filled PTFE: The 77 GHz Standard

Adding ceramic fillers to PTFE creates materials with engineered Dk values (2.94-10.2), improved mechanical stability, and reduced CTE. Rogers RO3003 (Dk = 3.0, Df = 0.0013) has become the dominant choice for 77 GHz automotive radar because it eliminates glass weave effects while matching copper's thermal expansion closely.

These materials still require specialised processing but offer tighter Dk tolerances (±0.04) than pure PTFE.

### Why RO3003 Dominates Automotive Radar

Six properties matter critically at 77 GHz:

- **Dk tolerance** ±0.04 for consistent antenna patterns
- **Very low Df** (0.0013) for acceptable link budgets
- **Smooth copper surfaces** (VLP or HVLP foils) to reduce conductor loss
- **Stable TCDk** (-3 ppm/°C) for temperature swings
- **Low moisture absorption** (<0.04%) for outdoor reliability
- **No glass weave effects** that cause signal variation

Materials must meet AEC-Q200 passive component qualification, with extended temperature range testing (-40°C to +125°C), 1500+ thermal cycles, and 85°C/85% RH humidity resistance.

---

## Hydrocarbon Ceramics: FR-4 Processing with RF Performance

The Rogers RO4000 series revolutionised RF PCB manufacturing by delivering good high-frequency performance (Dk 3.38-3.66, Df 0.0027-0.0037) with FR-4-compatible processing. No plasma treatment, no sodium etch, no specialised equipment - just standard PCB fabrication.

This makes RO4003C and RO4350B the workhorses for commercial applications from 500 MHz to 15 GHz, including 5G sub-6 GHz infrastructure and power amplifiers.

### Rogers RO4000 Series Comparison

| Material | Dk (Process) | Dk (Design) | Df @ 10 GHz | CTE (X;Y;Z) | Key Feature |
|----------|--------------|-------------|-------------|-------------|-------------|
| RO4003C | 3.38 | 3.55 | 0.0027 | 11;14;46 | Lowest loss in series |
| RO4350B | 3.48 | 3.66 | 0.0037 | 14;16;32 | UL 94 V-0 rated |
| RO4835 | 3.48 | 3.66 | 0.0031 | 14;16;32 | High oxidation resistance |
| RO4360G2 | 6.15 | 6.40 | 0.0038 | 10;12;30 | High-Dk, UL rated |

**Note on Dk values:** Rogers provides both "process" Dk (for manufacturing) and "design" Dk (for simulation). Use the design value for impedance calculations.

### Processing Advantage

The major advantage of hydrocarbon ceramic materials is FR-4-compatible processing:

- Standard drilling parameters work (300-500 SFM surface speed, 0.002-0.004"/rev chip load)
- No plasma treatment or special desmear required
- Compatible with standard develop-etch-strip systems
- Lower fabricator qualification barriers

---

## Advanced Thermoset Materials: The Best of Both Worlds

Isola's Astra MT77 exemplifies a new generation of ultra-low-loss thermoset materials achieving Df of 0.0017 with FR-4-compatible processing - approaching PTFE electrical performance without PTFE fabrication headaches.

| Material | Manufacturer | Dk | Df @ 10 GHz | Processing | Target Application |
|----------|--------------|-----|-------------|------------|-------------------|
| Astra MT77 | Isola | 3.0 | 0.0017 | FR-4 compatible | 77 GHz radar, mmWave 5G |
| mmWave77 | Shengyi | 3.06 | 0.001 | FR-4 compatible | 77 GHz radar (cost-optimised) |
| TerraGreen 400G | Isola | 3.05-3.15 | 0.0018 | FR-4 compatible | Halogen-free mmWave |

These materials support frequencies to 110 GHz and integrate well with high-speed digital materials for hybrid RF/digital designs.

---

## Critical Electrical Properties Explained

### Dk Tolerance Determines Impedance Repeatability

The Dk tolerance - not just the Dk value - determines whether designs will meet impedance specifications across production volumes. A material with Dk = 3.50 ± 0.05 enables predictable 50Ω traces. A material with Dk = 4.3 ± 0.5 (like standard FR-4) creates impedance swings that cannot be compensated through trace width adjustments alone.

**Practical guideline:** For frequencies above 10 GHz, specify materials with Dk tolerance ≤±0.05. For mmWave beam-forming applications, tighten this to ±0.02-0.04.

| Material | Dk @ 10 GHz | Tolerance | Impedance Impact |
|----------|-------------|-----------|------------------|
| RT/duroid 5880 | 2.20 | ±0.02 | Best available |
| RO3003 | 3.00 | ±0.04 | Excellent control |
| RO4350B | 3.48 | ±0.05 | ±2-3Ω on 50Ω |
| Standard FR-4 | 4.3-4.7 | ±0.2-0.5 | Unusable for RF |

### Dissipation Factor Thresholds by Application

Different applications have dramatically different Df requirements:

| Application | Frequency | Maximum Df | Typical Material |
|-------------|-----------|------------|------------------|
| Consumer WiFi/BLE | 2.4-5 GHz | 0.02 | FR-4 acceptable |
| 5G sub-6 GHz | 2.4-6 GHz | 0.004 | RO4350B, RO4003C |
| 5G mmWave | 24-39 GHz | 0.002-0.0035 | RO3003, Astra MT77 |
| 77 GHz automotive radar | 76-81 GHz | 0.0015 | RO3003 (Df = 0.0013) |
| Satellite Ka-band | 26.5-40 GHz | 0.001 | RT/duroid 5880 |

### Temperature Stability (TCDk)

The temperature coefficient of Dk (TCDk) determines how much impedance drifts with temperature swings. RO3003's exceptional TCDk of -3 ppm/°C means Dk barely changes from -40°C to +150°C. Standard FR-4 at +200 to +400 ppm/°C causes substantial drift.

**Target TCDk < 50 ppm/°C** for outdoor base stations, automotive radar, and power amplifiers.

---

## Hybrid Stackup Strategies

Combining RF materials with FR-4 in hybrid stackups can reduce material costs by 40-70% while maintaining RF performance where it matters. The key is placing high-frequency materials only on layers carrying RF signals.

### Example: Symmetric RF Outer Layers

```text
Layer 1:  RO4003C (0.020") - RF signals
Layer 2:  Ground plane
Layer 3-4: FR-4 core - digital/power
Layer 5:  Ground plane
Layer 6:  RO4003C (0.020") - RF signals
```

**Critical:** Keep stackups symmetric to prevent warping. Asymmetric constructions cause boards to bow during lamination and thermal cycling.

### Bondply Selection

Rogers RO4450F bondply provides reliable bonding between RO4000 laminates and FR-4 cores:

- Bond temperature: 177°C (FR-4 compatible)
- Lamination pressure: 200-750 PSI
- High Tg (>280°C) allows multiple lamination cycles

For dissimilar materials, target Dk difference ≤0.3 between bonded layers and use modified low-Dk FR-4 (such as Megtron 6 or I-Speed) for digital layers.

---

## Bonding Films and Prepregs Reference

| Type | Supplier | Thickness (mils) | Dk @ 10 GHz | Df @ 10 GHz | Lamination Temp | Use |
|------|----------|------------------|-------------|-------------|-----------------|-----|
| PTFE adhesive | DuPont | 1.2 | 2.08 | 0.0005 | 327°C | PTFE bonding |
| FEP | DuPont | 0.5-2.5 | 2.06 | 0.001 | 260-280°C | PTFE bonding |
| R700 | Arlon | 1.5-3 | 2.35 | 0.0025 | 100°C | Low-temp bond |
| 6250 | Arlon | 1.5 | 2.32 | 0.0013 | 100°C | Low-temp bond |
| RO4450F | Rogers | 3-4 | 3.23 | 0.004 | 200-400°C | RO4000/FR-4 hybrid |
| 6002 Bond-Ply | Rogers | - | 2.94 | 0.0012 | 1700 psi | RO6000 bonding |
| Speedboard C | Gore | 1.5-4.5 | 2.7 | 0.004 | 100-350°C | High-reliability |
| 25N/25FR | Arlon | 6.5 | 3.25 | 0.0024 | 110°C | Halogen-free option |

---

## CTE Management and Via Reliability

Z-axis CTE mismatch between the laminate and copper causes plated through-hole barrel cracking during thermal cycling. Standard FR-4 with Z-CTE of 55-70 ppm/°C stresses copper barrels. RO4350B at 32 ppm/°C significantly improves reliability.

**Target Z-axis CTE < 50 ppm/°C** for high-reliability applications. For boards experiencing many thermal cycles (automotive, aerospace), consider increased copper plating thickness (>1.5 oz).

RT/duroid 6002 demonstrates exceptional reliability with more than 5,000 thermal cycles without via failure - its Z-axis CTE of 24 ppm/°C closely matches copper.

---

## Application Selection Guide

### 5G Infrastructure

**Sub-6 GHz massive MIMO** (2.4-6 GHz): RO4835 and RO4350B dominate commercial deployments. Key requirements include low passive intermodulation (PIM) for antenna arrays and thermal dissipation for power amplifiers.

**mmWave 5G** (28 GHz, 39 GHz): Tighter Dk tolerance (±0.02) becomes essential. RO3003 and RT/duroid 5880 provide the Df < 0.002 needed for acceptable link budgets.

### Automotive Radar (77 GHz)

The market has standardised on RO3003 and equivalent materials. Alternatives include:

- **RO3003G2** - Optimised for 77-81 GHz with smaller filler particles
- **Isola Astra MT77** - FR-4 process compatible
- **Shengyi mmWave77** - Cost-effective alternative

### Aerospace and Defence

Beyond electrical performance, applications demand MIL-PRF-31032 compliance, extended service life (15+ years), temperature cycling from -55°C to +125°C for 5000+ cycles, and full material traceability.

### Satellite Communications

Space-qualified materials must pass NASA ASTM E595 outgassing testing: Total Mass Loss < 1.0% and Collected Volatile Condensable Materials < 0.1%. PTFE and polyimide materials generally excel.

---

## Common Mistakes to Avoid

### Design Errors

**Asymmetric stackup:** Causes warping during lamination. Always mirror RF layers symmetrically.

**Wrong Dk in calculations:** Use "process Dk" or "design Dk" from manufacturer datasheets, not "measured Dk." These values can differ by 5-10%.

**Via stubs above 5 GHz:** Quarter-wave resonances degrade signals. Specify back-drilling for via stubs in any RF path above 5 GHz.

### Fabrication Errors

**Mechanical scrubbing of PTFE:** Damages surface uniformity. Use only chemical or plasma treatment.

**Reusing drill bits:** Ceramic fillers damage carbide edges. Use fresh drills; expect only 2,000-3,000 hits before replacement.

**Skipping bakeout:** Moisture or absorbed chemicals cause PTH failures. Bake panels at 115-125°C for 15-30 minutes before copper plating.

### Specification Errors

**Over-specifying tolerance:** Requesting ±5% impedance when ±10% suffices increases cost and scrap.

**Under-specifying material:** Calling out "Rogers" without a specific part number leaves material selection to the fabricator.

---

## Information Fabricators Need

When specifying RF materials, provide:

- Exact material part numbers (e.g., "RO4003C 0.020" LoPro")
- Complete layer-by-layer stackup with materials per layer
- Controlled impedance values and tolerance (±10% standard, ±5% for >10 GHz)
- Operating frequency range
- Reference plane assignments for each controlled impedance trace
- Special requirements (back-drilling, plasma treatment, surface finish)

---

## Frequently Asked Questions

### When does FR-4 stop working for RF?

Standard FR-4 has a practical ceiling around 1-2 GHz. Above this, its high Df (~0.02) causes unacceptable insertion loss, and its Dk instability (±10% variation) makes impedance control unreliable. For applications above 2 GHz, specify purpose-built RF materials.

### What's the difference between RO4003C and RO4350B?

RO4003C has lower loss (Df 0.0027 vs 0.0037) and is preferred when UL flammability rating isn't required. RO4350B carries UL 94 V-0 certification, making it necessary for consumer products and applications with flammability requirements. Both process like FR-4.

### Can any fabricator process PTFE materials?

No. PTFE processing requires specialised drilling equipment (high-RPM spindles), plasma or sodium naphthalene surface treatment, and modified plating processes. Verify your fabricator's PTFE capabilities before specifying RT/duroid or RO3000 series materials.

### How do I choose between RO3003 and Astra MT77 for 77 GHz?

RO3003 remains the industry standard with proven automotive radar heritage. Astra MT77 offers similar electrical performance (Df 0.0017 vs 0.0013) with FR-4-compatible processing - potentially simplifying fabrication and reducing cost. If your fabricator can process RO3003 reliably, it's the safe choice. If PTFE processing is a concern, Astra MT77 is worth evaluating.

### What Dk value should I use for impedance calculations?

Use the "design Dk" value from manufacturer datasheets, measured at a frequency close to your operating frequency. For Rogers materials, design Dk is optimised for impedance calculations, while process Dk is for manufacturing. The difference can be 5-10%.

### Are Asian material suppliers competitive with Rogers and Isola?

Yes. Shengyi (mmWave77), ITEQ, and Doosan now offer materials genuinely competitive for high-frequency applications. About 70% of high-speed CCL production is now based in Asia. For cost-sensitive high-volume applications, these alternatives deserve evaluation.

---

## When to Consider Each Material Type

**RO4003C/RO4350B:**
- Frequency range 500 MHz - 15 GHz
- Standard PCB fabrication available
- Cost-performance balance required
- Mixed RF/digital designs

**RO3003/RO3003G2:**
- Frequency above 20 GHz
- 77 GHz automotive radar
- Tight Dk tolerance critical
- Fabricator has PTFE capability

**RT/duroid 5880:**
- Lowest possible loss required
- Satellite and space applications
- Phase-sensitive antenna arrays
- Cost secondary to performance

**Astra MT77/mmWave77:**
- mmWave frequencies with FR-4 processing
- PTFE capability limited
- Cost optimisation for high-volume
- Hybrid RF/digital integration

---

## Related Articles

- [RF and Microwave PCB Fabrication](/rf-microwave-pcb-fabrication/) - Delivered experience with Rogers-family and hybrid RF/FR-4 builds
- [PCB Materials and Laminates Guide](/technical-library/pcb-materials-guide/) - Complete laminate specifications
- [Controlled Impedance PCB Design](/technical-library/controlled-impedance-pcb-design/) - How Dk affects impedance
- [PCB Capability Limits](/technical-library/pcb-capability-limits/) - Manufacturing specifications

---

**Planning an RF or microwave board?** Review our [RF and microwave PCB fabrication experience](/rf-microwave-pcb-fabrication/), then send the stackup or performance requirements for a technical review.

---

<a id="rohs-effect-on-pcbs"></a>

## The Impact of RoHS on PCBs and Other Components

RoHS, the lead-free directive, restricts the use of hazardous materials in electronics manufacturing. When complying with this regulation, manufacturers must use lead-free solder, which operates at higher temperatures—270°C instead of the traditional 250°C used with lead-based solder.

## Temperature Impact on Materials

This 20-degree temperature increase makes PCB material selection critical to avoid delamination or "pop-corning" during the soldering process. The key factor to consider is the **glass transition temperature (Tg)** of the laminate material.

## Glass Transition Temperature (Tg) Requirements

- **Traditional lead-based soldering:** Tg 130-140°C was typically sufficient
- **Lead-free processes:** Now typically require Tg 150°C or Tg 170°C materials

## Moisture Considerations

Trapped moisture in laminates can cause damage during the higher-temperature lead-free soldering process. To prevent this:

- Store PCBs and components properly to minimize moisture absorption
- Pre-bake components and boards before soldering when necessary
- Consider using moisture-barrier packaging for sensitive materials

## Material Selection

Selecting the appropriate material for your specific application is crucial for RoHS compliance. The right choice depends on:

- The complexity of the assembly process
- The number of reflow cycles required
- The operating environment of the final product
- Cost considerations

For guidance on selecting the right materials for your RoHS-compliant PCB design, please [contact our team](/contact/).

---

## Related Articles

- [PCB Materials and Laminates Guide](/technical-library/pcb-materials-guide/) – Tg ratings and material specifications
- [How Multilayer PCBs Are Made](/technical-library/how-to-build-pcbs/) – Understanding the lamination and soldering processes
- [PCB Designer's Tips](/technical-library/pcb-designers-help/) – Material selection considerations

---

**Questions about RoHS-compliant materials?** [Request a quote](/quote/) – we'll recommend the appropriate Tg material for your assembly process.

---

<a id="solder-mask-via-types"></a>

## Solder Mask and Via Types

## The Problem: Open Vias Cause Assembly Defects

Uncovered via holes create problems during assembly. Solder wicks down into open vias, starving the joint above. Flux residue gets trapped in holes, causing reliability issues. Vacuum test fixtures can't seal against boards with open vias. And under fine-pitch BGAs, open vias can short to adjacent balls.

The solution is controlling how solder mask interacts with your vias—and there are several options depending on your requirements.

## Via Covering Options

![Diagram showing four different solder mask treatments for via holes: open, tented, plugged, and filled](/assets/images/technical-library/type-of-solder.webp)

*Via covering options: from fully open (left) to fully plugged (right)*

### 1. Open Vias (No Mask)
Solder mask is pulled back from the via, leaving the hole fully exposed.

**Use when:**
- Via is a test point
- Intentional solder fill is required
- Via is far from components

**Problems:**
- Solder wicking during assembly
- Flux entrapment
- Shorts under BGAs

### 2. Tented Vias
Solder mask covers the via opening like a tent. The via remains hollow underneath.

**Use when:**
- Via is near components but not under them
- Basic protection from solder wicking is sufficient
- Lowest cost option

**Limitations:**
- Tent may have small holes (mask doesn't perfectly bridge)
- Not suitable for vacuum test fixtures
- Can trap air during wave soldering

### 3. Plugged Vias (Mask Filled)
Via is filled with solder mask material, not just tented over.

**Use when:**
- Vacuum test fixtures require sealed surface
- Via is close to (but not directly under) solder paste
- Better sealing than tenting required

**Process note:** Fill from one side only to avoid trapping air.

### 4. Filled and Capped Vias
Via is filled with epoxy or conductive fill, then plated over. Results in a flat, solderable surface.

**Use when:**
- Via-in-pad designs (via directly in component pad)
- BGAs requiring vias under the package
- Maximum reliability and flatness required

**Cost:** Highest option due to additional processing steps.

## Solder Mask Defined (SMD) Pads

For fine-pitch components, an alternative approach uses the solder mask to define the solderable pad area:

![Comparison diagram showing standard solder mask opening versus solder mask defined pad opening, with dimensions](/assets/images/technical-library/screenshot-solder-mask-opening.webp)

*Left: Standard pad (mask opening larger than copper). Right: Solder mask defined pad (mask overlaps copper edge)*

### Standard Pads (NSMD)
- Solder mask opening is larger than the copper pad
- Solder fillet wraps around pad edge
- Most common approach

### Solder Mask Defined Pads (SMD)
- Solder mask overlaps the pad edge
- Solder is confined to the mask opening
- Allows tighter pitch (mask controls spacing, not copper etching)

**Example:** 0.5 mm pitch BGA with 0.25 mm pads
- Copper pad spacing: 0.1 mm (challenging to etch reliably)
- With SMD: Copper can be larger, mask defines the 0.25 mm opening

**Trade-off:** SMD pads have smaller solder fillets and slightly lower joint strength, but enable finer pitches.

## Design Guidelines

### Under BGAs
- Never leave vias open under BGA packages
- Via-in-pad requires filled and capped vias
- Dog-bone vias (outside pad) can be tented or plugged

### For Test Fixtures
- Vacuum fixtures require plugged vias (one side)
- Flying probe testing can work with any via type

### Spacing Rules
| Via Treatment | Minimum Spacing to Pad |
|---------------|------------------------|
| Open via | 10 mil (avoid under components) |
| Tented via | 6 mil |
| Plugged via | 4 mil |
| Filled/capped | 0 (via-in-pad allowed) |

---

## Related Articles

- [BGA Component Design Guide](/technical-library/bga-component-facts/) – BGA pad and solder mask considerations
- [Multilayer PCB Capabilities](/technical-library/pcb-capability-limits/) – Solder mask specifications
- [PCB Designer's Tips](/technical-library/pcb-designers-help/) – Design guidelines for manufacturability

---

**Questions about solder mask options?** [Request a quote](/quote/) – we'll recommend the best approach for your design.

---



================================================================================

# PCB Build Illustrations

Reference stackup diagrams for standard PCB constructions. Each build shows layer arrangement, material thicknesses, and typical applications.

## Rigid PCB Builds

### R7000 Series - Standard Multilayer

Standard multilayer constructions using FR-4 materials.

- **R7001**: 4-layer, 1.6mm, 1oz copper
- **R7002**: 6-layer, 1.6mm, 1oz copper
- **R7003**: 8-layer, 1.6mm, 1oz copper
- **R7004**: 10-layer, 2.0mm, 1oz copper
- **R7005**: 12-layer, 2.4mm, 1oz copper

### R7010 Series - High-Tg Multilayer

High-temperature constructions for lead-free assembly and demanding environments.

- **R7011**: 4-layer high-Tg, 1.6mm
- **R7012**: 6-layer high-Tg, 1.6mm
- **R7013**: 8-layer high-Tg, 1.6mm

### R7020 Series - HDI Constructions

High-density interconnect with micro-vias and fine features.

- **R7021**: 1+4+1 HDI, laser micro-vias
- **R7022**: 2+4+2 HDI, stacked micro-vias
- **R7023**: 1+6+1 HDI, any-layer
- **R7024**: 2+8+2 HDI, any-layer

## Flex and Rigid-Flex

Flexible circuit constructions available on request. Contact us for custom stackup design.

## Custom Stackups

We design custom stackups for:
- Controlled impedance requirements
- Specific material systems
- Thermal management
- EMI/EMC compliance

Contact us at https://ship.ie/quote/ with your requirements.